Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-05-04
2002-12-03
Jones, Hugh M. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S004000, C703S005000
Reexamination Certificate
active
06490546
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to a circuit simulation program and, more specifically, to a method for obtaining DC convergence for silicon-on-insulator (SOI) field effect transistors (FETs) models in the steady state DC phase of a circuit simulation program.
BACKGROUND OF THE INVENTION
Circuit simulation programs make use of device models to simulate single devices or large circuits consisting of many devices. These circuit simulation programs use standard numerical methods to solve an underlying system of equations (e.g. algebraic).
A typical circuit simulation consists of several phases. Usually in the first phase a steady state DC analysis is performed to compute the initial operating point (e.g. currents, voltages, charges) for each of the circuit elements. When the circuit simulation program successfully completes the DC analysis, it is said to have achieved “DC convergence.” A second phase, known as the transient analysis phase, is often conducted to compute the changes in the circuit currents and voltages as a function of time. Alternatively, the second phase might be a frequency analysis phase which computes the frequency dependence of the circuit. In some cases, the desired information is obtained from the DC analysis, in which case a second phase is not needed.
Circuit simulation programs use iterative methods for solving the circuit equations. For example, in the steady state DC phase (hereinafter “DC phase”) of the analysis, the program starts by assuming an initial operating point for all the circuit elements. That is, an initial set of voltages, currents, and charges is chosen. The program then allows a small amount of time to pass and calculates the changes in the operating point for all the circuit elements. The amount of time is called the “pseudo-time step.” The qualifier “pseudo” is used since during a DC analysis the “real” time has not changed. In this discussion, we will use the phrase “time step” with the understanding that it refers to a “pseudo-time step” during a DC analysis. The program then uses the previous result to choose a new operating point and time step, and repeats the calculations. Each repeat of the calculations is called an “iteration.”
After each iteration, the changes in the voltages, currents, and charges are compared to an error criteria. If any of these changes are greater than the error criteria, the program continues with another iteration. If all of these changes are less than the error criteria then the program stops. At this point, when all of the error criteria are met, “DC convergence” is achieved. All of the voltages, currents, and charges have reached their steady state, DC values. If the program continues without ever meeting the error criteria, or stops for any other reason, then there is a failure to achieve DC convergence.
During a second transient analysis phase, the program proceeds in a similar manner except that “real-time” steps are used instead of “pseudo-time” steps. Circuit analysis programs are controlled by an input dataset, also known as a source or a netlist, and typically consist of at least three main components or sections. In the AS/X and PowerSPICE circuit simulation programs, the three components are the model description, execution controls, and outputs.
The description of the circuit and the details of the circuit models are given in the model description section. The execution controls section contains instructions that specify the analysis phases to be run, and the run controls which specify how the analysis is to be carried out. The outputs section specifies the information to be returned from the program.
A device model consists of a set of circuit elements which stimulate the operation of a device, such as a field effect transistor (FET). The basic components of an FET, as illustrated in
FIGS. 1 and 2
, include a source
10
, drain
12
, gate
14
, and body region
16
. The substrate
1
is made of those materials conventionally used, such as silicon, and often contains a doped well region containing the source, drain and body regions of the FET. An optional oxide region
30
provides lateral electrical isolation of the device.
The voltages of the source, drain, gate, and body regions determine the currents which flow through the FET. As a result, it is important to accurately model and simulate these voltages.
The FET in
FIG. 1
is illustrative of a “bulk” device in which the substrate or well region
1
is either electrically grounded or connected to a fixed power supply voltage. For this FET, the body region
16
is contiguous with substrate or well region
1
. Thus, the electrical ground or power supply connection provides a stable, known voltage for the body region
16
. As a result, circuit simulation programs do not have a problem solving for the operating point associated with the body region of these bulk FETs.
Recently, it has become desirable to use FETs formed on a silicon-on-insulator (SOI) substrate, an example of which is illustrated in FIG.
2
. SOI substrates have an oxide layer
18
, which is an electrical insulator, separating body region
16
from substrate
1
. As a result, the body region of the SOI FET is not electrically connected to a stable ground or power supply voltage. In this case, the body region is often referred to as a “floating body” region. The voltage of this floating body region is sensitive to small DC leakage currents which enter or leave from the source and the drain to the floating body region, and is also sensitive to small capacitive currents between the floating body region and the source, drain, gate, and substrate. The sensitivity of the floating body region creates difficulty in achieving DC convergence in circuit simulation programs, or if convergence is achieved, the resulting solution is often incorrect. This problem is exacerbated with circuits containing many SOI FETs, the design of which is becoming increasingly common.
The deficiencies of the use of conventional circuit simulation programs show that a need exists for obtaining accurate DC convergence in the DC phase for SOI FET models. To overcome the shortcomings of conventional methods, a new process is provided. An object of the present invention is to provide a method of obtaining accurate DC convergence in the DC phase for SOI FET models in a circuit simulation program.
SUMMARY OF THE INVENTION
To achieve these and other objects, and in view of its purposes, the present invention provides a method for obtaining an accurate DC convergence in the DC phase of a circuit simulation program for field effect transistors (FETs) of a silicon-on-insulator (SOI) substrate.
The method of the invention comprises setting a desired current value and running the steady state phase of a circuit simulation program, simulating circuits containing models of silicon-on-insulator (SOI) field effect transistors (FETs), and requiring that iterations continue until the error criteria are met, and also requiring that iterations continue until the size of the pseudo-time step has increased to a value such that the desired current value is achieved. Both of these conditions are required to achieve DC convergence. The large final value of the pseudo-time step helps the simulator achieve DC convergence, and in addition, assures that a correct solution is found.
Preferably, the size of the pseudo-time step in the DC phase of the simulation is controlled by modifying an algorithm in the circuit analysis program so that the size of the pseudo-time step changes with each iteration until it reaches a sufficiently large value such that the desired current value is achieved. The size of the large value is preferably specified by a run control in the circuit simulation program.
In a second embodiment of the invention, a desired current value is selected and the values for the capacitive and/or charge elements in the field effect transistors (FET) on a silicon-on-insulator (SOI) substrate model are reduced during the steady state DC analysis to achieve the desired current value. At the end of the
Kimmel Richard
Wagner, Jr. Lawrence F.
Jones Hugh M.
Ratner & Prestia
Townsend, Esq. Tiffany L.
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