Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2008-11-03
2010-06-08
Hoang, Huan (Department: 2827)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185120, C365S185030
Reexamination Certificate
active
07733703
ABSTRACT:
Part of the latency from memory read or write operations is for data to be input to or output from the data latches of the memory via an I/O bus. Methods and circuitry are present for improving performance in non-volatile memory devices by allowing the memory to perform some of these data caching and transfer operations in the background while the memory core is busy with a read operation. A read caching scheme is implemented for memory cells where more than one bit is sensed together, such as sensing all of the n bits of each memory cell of a physical page together. The n-bit physical page of memory cells sensed correspond to n logical binary pages, one for each of the n-bits. Each of the binary logical pages is being output in each cycle, while the multi-bit sensing of the physical page is performed every nth cycles.
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Davis , Wright, Tremaine, LLP
Hoang Huan
Sandisk Corporation
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