Multiplex communications – Miscellaneous
Reexamination Certificate
1999-06-07
2004-01-13
Cangialosi, Salvatore (Department: 2732)
Multiplex communications
Miscellaneous
C370S529000
Reexamination Certificate
active
06678287
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to digital circuitry within a computer system. More specifically, the present invention relates to a system for multiplexing multiple signal lines through an I/O pin on a semiconductor chip.
2. Related Art
Much of the interconnection circuitry in a microprocessor-based computer system is typically aggregated in a “core logic” unit that couples the microprocessor to other parts of the computer system, such as a memory, a peripheral bus and a graphics controller.
Providing such interconnection capability can require a large number of I/O pins to accommodate all of the signal lines. Some computer systems deal with this I/O pin problem by partitioning interconnection circuitry across multiple chips. For example, a typical personal computer system includes a north bridge chip, a south bridge chip, a super I/O chip and an I/O APIC chip to support interconnections between the microprocessor and other components within the computer system. Using multiple chips is expensive because the multiple chips must be integrated together within a circuit board. This leads to additional expense in manufacturing circuit boards and maintaining inventories of each type of chip.
It is preferable to integrate all of the interconnection circuitry in a computer system into a single semiconductor chip. However, I/O pin limitations on a single chip can present problems. For example, a single core logic chip that includes all of a computer system's interconnection circuitry requires interfaces for a processor bus, a memory bus, an AGP bus for a graphics controller and a PCI bus for peripheral devices. Providing I/O pins for all of these interfaces requires many hundreds of I/O pins, especially if any of the busses support 64 bit transfers. This I/O pin requirement can easily exceed the I/O pin limitations of a single semiconductor chip.
It is desirable to somehow compress the signal lines feeding into a core logic chip so that they flow through a smaller number of I/O pins. One method of accomplishing this is to multiplex signal lines by using additional multiplexer select signals. For example, three extra select lines can be used to multiplex eight signal lines through a single I/O pin. However, these extra select signals require additional I/O pins, which somewhat defeats the purpose of the multiplexing in the first place.
What is needed is a system that multiplexes multiple signal lines through a single I/O pin without using additional I/O pins for select signals.
SUMMARY
One embodiment of the present invention provides a method for selectively multiplexing a plurality of signal lines through an I/O pin on a semiconductor chip. The method starts by initializing a transmitting circuit and a receiving circuit to selectively multiplex the plurality of signal lines from the transmitting circuit through the I/O pin and into the receiving circuit. This initialization process includes selecting at least one of the plurality of signal lines to be multiplexed through the I/O pin, as well as synchronizing the transmitting circuit and the receiving circuit by asserting a reset signal. Once the transmitting and receiving circuits are initialized, the selected signal lines are multiplexed from the transmitting circuit through the I/O pin and into corresponding memory elements in the receiving circuit. Note that the transmitting circuit and the receiving circuit are driven by a common clock signal.
REFERENCES:
patent: 4758747 (1988-07-01), Young et al.
patent: 5336951 (1994-08-01), Josephson et al.
patent: 5664140 (1997-09-01), Klein
patent: 5671433 (1997-09-01), Fung et al.
patent: 5811987 (1998-09-01), Ashmore et al.
patent: 6256767 (2001-07-01), Kuekes et al.
Cangialosi Salvatore
Micro)n Technology, Inc.
Park Vaughan & Fleming LLP
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