Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support
Reexamination Certificate
2000-07-31
2002-08-20
Christianson, Keith (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Insulative housing or support
C438S612000, C257S701000
Reexamination Certificate
active
06436735
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to the packaging of semiconductor devices, and more particularly to a system and method for interconnecting integrated circuits (ICs) on a semiconductor substrate.
Electronic systems typically are manufactured from two or more ICs to provide complete system function. Until recently the limitations on performance and number of I/O pins were not significant for the vast majority of applications. However, as more devices are integrated in a single IC and as clock speeds increase, limitations on performance and number of I/O pins would be of paramount concern to semiconductor manufacturers. This is because the overall performance of the system is based on multiple ICs is a function of the performance of the individual ICs and of the performance of the signals between the ICs. The performance of the signals between the ICs is in turn a function of the number of signals and the electrical characteristics of the means used to connect the I/O pins of the ICs. A more efficient means for interconnecting ICs is, therefore, becoming an important influence on the cost, size, performance, weight, and efficiency of electronic systems.
Currently, the most common method used for interconnecting ICs is to first package the individual ICs, and then mount the packaged ICs on a substrate such as a printed circuit board. The size of the package is typically several times larger than the IC and is often manufactured from a metal lead frame and protected within a plastic molded case. The packaged ICs are then placed and soldered to a printed circuit board to create a complete electronic system. The advantages of the current method include low cost and protection of the IC during subsequent handling. In addition, the package acts as a standardized carrier for testing of the IC, such that design changes to the printed circuit board may be made cheaply and quickly. Assembly of the IC to the printed circuit board may further be automated. Finally, the current system allows rework of the printed circuit.
A more efficient method of interconnecting ICs has been demonstrated with the use of flip-chip technology in which a silicon substrate having metallization is connected to an integrated circuit via solder connections. This type of coupling between the integrated circuit and the substrate allows increasing the number of I/O pins, compared to other interconnect technology. A drawback with traditional flip-chip technologies concerns the degradation of the electrical connections subsequent to repeated thermal cycling.
What is needed, therefore, is a mounting technique for integrated circuits that facilitates increased I/Os while avoiding thermal degradation of the I/O substrate interface.
SUMMARY OF THE INVENTION
Provided is a mount for an integrated circuit and a process for manufacturing the same that features a routing carrier having a power plane, a conductive bond pad spaced-apart from the power plane and an insulative body disposed therebetween. The insulative body includes a via extending between the power plane and the conductive bond pad with a metallic contact disposed therein. The metallic contact and the bond pad have circular cross-sections, with a ratio of the diameter of the bond pad to the diameter of the metallic contact being in the range from 2:1 to 5:4, inclusive, i.e, the solder pad would be anywhere from 125% to 200% larger than the via diameter. The present invention is based upon the discovery that degradation of the electrical connection between the routing carrier and an integrated circuit mounted thereto results from cracking of the metallic contact. To solve this problem the relative size of the bond pad to metallic contact was found to be critical. Specifically, it was determined critical that the diameter of the bond pad and the diameter of the metallic contact have the aforementioned ratio. With this structure, the stress to which the metallic contact is subjected to by the solder bump is controlled when disposing the solder bump on the bond pad employing electroplating techniques, because it allows controlling the size of the solder bump on the bond pad. When disposing the solder bump using electroplating techniques, the solder bump takes a hemispherical shape. A sufficient amount of solder is provided so that the diameter of the solder bump is approximately equal to the diameter of the bond pad.
One embodiment of the present invention is described as being used in conjunction with a plurality of routing carriers formed from silicon, each of which has an IC attached thereto. A semiconductor board, typically formed from silicon has a plurality of signal traces and a plurality of bond sites disposed thereon, with the plurality of bond sites enclosing a region of the insulative member. A subset of the plurality of signal traces are associated with the plurality of bond sites so that each of the signal traces of the subset extends from one of the plurality of bond sites, away from the region, defining an electrically nonconductive area. The conductive bond pads on the routing carriers superimposes the subset of bond sites enclosing the region so that each of the subset of bond pads superimposes one of the subset of bond sites, when placed in a final seating position. The routing carrier includes a plurality of conductive traces, a subgroup of which superimposes the nonconductive area and extends between a pair of bond pads so as to place a pair of the bond sites in electrical communication. The integrated circuit is coupled to a subset of the remaining bond pads of the routing carrier and is positioned thereon so as to superimpose the nonconductive area. The nonconductive area typically comprises an aperture having an area which exceeds a cross-sectional area of the integrated circuit, with the integrated circuit being positioned on the routing carrier so as to fit within the aperture, upon the routing carrier reaching a final seating position with the board.
These and other embodiments of the present invention, along with many of its advantages and features, are described in more detail in the text below and the attached figures. In the figures, like reference numerals indicate identical or functionally similar elements.
REFERENCES:
patent: 4888665 (1989-12-01), Smith
patent: 5148266 (1992-09-01), Khandros et al.
patent: 5371403 (1994-12-01), Huang et al.
patent: 5457340 (1995-10-01), Templeton, Jr. et al.
patent: 5483100 (1996-01-01), Marrs et al.
patent: 5541450 (1996-07-01), Jones et al.
patent: 5557502 (1996-09-01), Banerjee et al.
patent: 5628919 (1997-05-01), Tomura et al.
patent: 5708296 (1998-01-01), Bhansali
patent: 5883428 (1999-03-01), Kabumoto et al.
Todd Takken and David Tuckerman, “Integral Decoupling Capacitance Reduces Multichip Module Ground Bounce,” Proceedings of 1993 IEEE Multi-Chip Module Conference, pp. 79-84, Jan. 1993.
Avery George E.
Beal Sam
Brown Sammy K.
Goetz Martin P.
Todd Tom L.
Alpine Microsystems, Inc.
Brooks Kenneth C.
Christianson Keith
Smoot Stephen W.
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