Data processing: generic control systems or specific application – Generic control system – apparatus or process – Having protection or reliability feature
Reexamination Certificate
2001-05-09
2003-11-18
Patel, Ramesh (Department: 2121)
Data processing: generic control systems or specific application
Generic control system, apparatus or process
Having protection or reliability feature
C700S001000, C714S715000, C702S108000
Reexamination Certificate
active
06650950
ABSTRACT:
FIELD OF AND BACKGROUND OF THE INVENTION
The invention relates to a method for monitoring an output function of an output unit. More specifically, the output unit can be a binary signal output unit of a safety-oriented programmable logic controller, which controls actuators of an external technical process.
Safety-oriented binary signal output units, which have a respective read-back circuit for each output, are known in the art. These read-back circuits verify the correct functioning of the respective output by check-reading. The output bit patterns produced by the external technical process are checked by a target/actual comparison. In addition, if the dynamics of the output signals are low, Supplementary Tests are required, which must be executed within prescribed time intervals in order to assure operational safety. Conventional binary signal output units use the following two test strategies.
First, the highest test quality is obtained by applying a complete set of test bit patterns to the output unit and by check-reading these test bit patterns. In this complete test, it is disadvantageous that, during short test pulses, a voltage is applied to the actuators. This can reduce the life span of the actuators, in particular in view of the frequency of the test pulses.
Second, an intermediate test quality is obtained if, for each enabling signal that is transmitted to the external technical process via the output of the output unit, the capability of the output for transmitting a disabling signal is checked. This creates short interruptions of the controlled actuators, which can also reduce the life span of the actuators.
Both tests have the further disadvantage that they cause frequent switching of currents that are caused by loads in the system. In particular, this disadvantage has become noticeable in recently developed, technically advanced output units. In the past, simple-structured output units predominated, whose Supplementary Test could be implemented by a small number of different test patterns. Nowadays, however, the safety-oriented output units increasingly have ASICs and microprocessors or microcontrollers. For these structures, pattern-sensitive tests are prescribed. This causes a significant increase in the number of test patterns. The frequency of the test patterns has other negative effects on the technical environment, such as EMC interference, increased energy consumption, increased noise development, and mechanical vibrations.
OBJECTS OF THE INVENTION
It is one object of the present invention to reduce the number of the bit patterns that are applied to the output unit and that are check-read when the Supplementary Test is carried out.
SUMMARY OF THE INVENTION
According to one formulation of the present invention, this and other objects are achieved in that an output function of an output unit is checked within a predetermined time interval. To this end, only those bit patterns are used that have not been transmitted by the output unit to actuators of an external technical process within that predetermined time interval. Therein, the output unit controls the actuators of the external technical process.
According to another formulation of the present invention, this and other objects are achieved by commencing a predetermined time interval and by executing an external technical process. Therein, actuators are controlled with operational bit patterns during the time interval and the operational bit patterns are compared with test bit patterns. An output function is checked with only those test bit patterns that do not coincide with the operational bit patterns.
The present invention includes preferred embodiments, which are related to each of the aforementioned test strategies. A first preferred embodiment reduces the number of test bit patterns in the aforementioned complete Supplementary Test. In the case of a predetermined total set of bit patterns, which are to be output and check-read within a time interval that is predefined based on safety requirements, the output bit patterns, which are produced by the external technical process, are balanced in a list. To this end, the output unit is provided with a memory, which stores all the bit patterns that are output in one time interval. In addition, only the bit patterns that have not yet occurred or have not yet been activated in the list are output and check-read in the form of test bit patterns. This balancing and activating of bit patterns must be re-executed in each time interval. At the start of each time interval, a time counter is reset and the list of bit patterns is cleared. The length of the time intervals is a function of the applicable safety requirements and is, for instance, one hour. If all the bit patterns to be checked are produced by the process within one time interval anyway, no further bit pattern needs to be applied and check-read for test purposes within that time interval. If, however, within one time interval, the output unit outputs, as a function of the external technical process, none of the predefined bit patterns to be checked, all the predefined test bit patterns are applied and check-read within that one time interval. In most cases, some of the bit patterns to be checked will be produced by the process so that the number of bit patterns that have to be applied and check-read for test purposes is reduced.
A second preferred embodiment according to the invention improves the aforementioned test of intermediate test quality. The output bit patterns produced by the process and the disabling test bit patterns are marked in a set point list or target list, which is reduced compared to the first test strategy. Other than that, the second preferred embodiment does not differ from the first preferred embodiment.
The method according to the present invention thus avoids a repeated output of test patterns for test purposes. Due to the method according to the present invention, the load on the actuators is reduced by up to 50% compared to conventional Supplementary Tests. This prolongs the life span of the actuators and reduces the previously mentioned disadvantages encountered in the prior art, e.g., EMC interference, increased energy consumption, noise development and mechanical vibrations.
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Mueller Manfred
Ringler Andrea
Schinnerl Johann
Schuetz Hartmut
Hartman Jr. Ronald D
Patel Ramesh
Siemens Aktiengellschaft
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