Method for modifying a fault-tolerant processing system

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371 683, 371 54, 371 91, G06F 1120, G06F 1540

Patent

active

052874923

ABSTRACT:
A method for modifying a fault-tolerant processing system (FTS) including a pair of partner sets of two processors (PA1/PA2; PB1/PB2) operating in microsynchronization at a first or low processing frequency (FL) and connected to a respective system bus (BA; BB) operating at a bus clock frequency (FB) lower than the first processing frequency (FL). The method consists in:

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