Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Target device
Reexamination Certificate
2006-07-11
2006-07-11
Rodriguez, Paul L. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Target device
C703S002000, C703S021000, C703S022000
Reexamination Certificate
active
07076417
ABSTRACT:
A method is disclosed for modeling and processing an asynchronous functional specification to provide an input to an architecture synthesis engine. The method includes the step of generating an initial task graph from the specification, the task graph having a number of executable tasks. Selected data and control connections are established between respective tasks in accordance with a specified set of rules to define some of the tasks to be deterministic, and other of the tasks to be non-deterministic. Each of the control connections is then marked, to provide an annotated task graph for use as an input to the architecture synthesis engine, the annotated task graph enabling the engine to employ specified scheduling techniques.
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Inventor(s): Jarrett Sime, Title: “A Synopsis of Parallel Processing Architecture and Operating System Design”, Date: Jan. 29, 2001, pp. 1-26.
Search Report under Section 17, Dated Mar. 6, 2003.
Biswas Chaitali
Jain Rajiv
Su Alan Peisheng
Agilent Technologie,s Inc.
Proctor Jason
Rodriguez Paul L.
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