Method for mitigating DC offset in a sign bit correlator

Details Method for mitigating DC offset in a sign bit correlator Method for mitigating DC offset in a sign bit correlator

2006-02-14

2006-02-14

Vo, Don N. (Department: 2631)

Pulse or digital communications

Receivers

Particular pulse demodulator or detector

C375S346000

Reexamination Certificate

active

06999534

ABSTRACT:
A method10is provided to mitigate DC offset in a sign bit correlator associated with a packet detection circuit. The input sign pattern is monitored; and if a long run of the same sign is seen, a sign bit is replaced with a bit generated using a desired pseudorandom noise (PN) sequence. This ensures that the correlator only reacts substantially to correlations that are not due to DC offset.

REFERENCES:
patent: 4379284 (1983-04-01), Boykin
patent: 5410368 (1995-04-01), Krishnamurthy et al.
patent: 5448571 (1995-09-01), Hong et al.
patent: 5757848 (1998-05-01), Hogberg
patent: 5793548 (1998-08-01), Zook

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