Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-01-09
2004-02-03
Chen, Kin-Chan (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S720000
Reexamination Certificate
active
06686289
ABSTRACT:
This application claims the benefit of Korean Application No. P2001-32310 filed on Jun. 9, 2001, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for minimizing a variation in an etch rate of a semiconductor wafer caused by a variation in a mask pattern density.
2. Discussion of the Related Art
Generally, to manufacture a semiconductor device, various processes such as a deposition process and an etching process are performed on a semiconductor wafer.
The etching process is performed in such a manner that a photoresist is deposited on the semiconductor wafer and then selectively removed from the semiconductor wafer using a reticle having a pattern. Thereafter, the semiconductor wafer is chemically etched or is etched by using a plasma so as to form a pattern.
Plasma etching equipment for processing a semiconductor wafer will be described with reference to FIG.
1
.
As shown in
FIG. 1
, a vacuum tight chamber
1
has a wafer stage
2
, a gas spray plate
3
, a coil
4
, a gas feeding line
5
, a bias power
6
, and a source power
7
. More specifically, at the bottom of the chamber
1
, a semiconductor wafer A
1
is mounted on the wafer stage
2
. The bias power
6
is applied to the wafer stage
2
. At the upper portion of the chamber
1
, the gas spray plate is supplied with a gas through the gas feeding line
5
and a coil
4
is applied by a source power
7
.
In the aforementioned plasma etching equipment for etching a semiconductor wafer, the semiconductor wafer A
1
is mounted on the wafer stage
2
within the chamber
1
. A gas is supplied through the gas spray plate
3
. The source power
7
providing a high voltage and the bias power
6
are applied to the coil
4
and the wafer stage
2
, respectively. Also, the gas supplied through the gas spray plate
3
forms a plasma having high oxidizing power within the chamber.
The semiconductor wafer A
1
is etched through the following processes; inserting the semiconductor wafer A
1
into the plasma etching equipment, supplying an etch gas and generating a plasma, diffusion and adsorption of the etch gas onto the semiconductor wafer W
1
, diffusion into the semiconductor wafer A
1
, reaction with the semiconductor wafer A
1
and desorption of by-products, and removal of the desorpted by-products.
Recently, in order to increase an etch rate and facilitate the control of an etching process a method for lowering an overall pressure of an etch gas and increasing a density of the plasma has been widely used.
Meanwhile, in the etching process using the plasma, an etch rate is varied with a variation of a mask pattern density.
Table 1 is a graph showing a variation in the etch rate of aluminum (Al) and photoresist (PR) according to the mask pattern density under the same conditions for 0.25 &mgr;m technology logic devices using the standard parameters; process pressure of 180 mT/system power of 500 Ws/50 G/BCl
3
flow rate of 60 sccm/Cl
2
flow rate of 40 sccm/N
2
flow rate of 40 sccm.
TABLE 1
Products
Metal 1
Metal 2
Metal 3
Metal 4
Metal 5
A
30.4%
30.8%
31.3%
25.8%
25.7%
B
29.2%
30.4%
36.3%
20.6%
18.9%
C
40.6%
56.5%
D
40.3%
32.7%
49.6%
E
24.2%
23.9%
30.1%
28.3%
27.2%
According to the results of Table 1 and
FIG. 2
, since the etch rate is varied with a change in the mask pattern density for each product, an etch characteristic for each product is varied. Therefore, it is necessary to develop the same process for each product even if products of the same 0.25 &mgr;m technology grade are developed.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method for minimizing a variation in an etch rate of a semiconductor wafer caused by a variation in a mask pattern density that substantially obviates one or more of problems due to limitations and disadvantages of the related art.
Another object of the present invention is to provide a method for minimizing a variation in an etch rate of a semiconductor wafer caused by a variation in a mask pattern density in which a parameter closely related to an amount of an etch gas is adjusted to reduce an effect of the mask pattern density.
Additional features and advantages of the invention will be set forth in the description which follows and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for minimizing a variation in an etch rate of a semiconductor wafer caused by a variation in a mask pattern density, the method including determining a reference amount of an etch gas in a reference mask pattern density, obtaining an optimized amount of the etch gas in a mask pattern density different from the reference mask pattern density, wherein the optimized amount is obtained by the following equation:
(
the
reference
amount
for
the
reference
mask
pattern
density
)
×
(
1
-
the
mask
pattern
density
)
(
1
-
the
reference
mask
pattern
density
)
,
and the mask pattern density is a value of dividing a mask pattern area by an overall semiconductor wafer area, and applying the optimized amount of the etch gas for an etching process of the semiconductor wafer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4784719 (1988-11-01), Schutz
patent: 4786361 (1988-11-01), Sekine et al.
patent: 5514247 (1996-05-01), Shan et al.
patent: 5552996 (1996-09-01), Hoffman et al.
patent: 5667630 (1997-09-01), Lo
patent: 5877032 (1999-03-01), Guinn et al.
patent: 6043001 (2000-03-01), Hirsh et al.
patent: 6054391 (2000-04-01), Nam et al.
patent: 6165907 (2000-12-01), Yoneda et al.
patent: 6372655 (2002-04-01), Khan et al.
Chen Kin-Chan
Hynix / Semiconductor Inc.
Morgan & Lewis & Bockius, LLP
LandOfFree
Method for minimizing variation in etch rate of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for minimizing variation in etch rate of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for minimizing variation in etch rate of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3354537