Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-08-08
2002-02-05
Hiteshew, Felisa C. (Department: 1765)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S734000, C438S739000, C438S749000, C438S753000
Reexamination Certificate
active
06344417
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates generally to micro-electro-mechanical systems (MEMS). More particularly, the present invention relates to a fabrication method for MEMS devices and for integrating, on a single chip, MEMS devices and semiconductor devices (e.g., CMOS, etc.).
BACKGROUND OF THE INVENTION
Surface micro-machining is a common processing technique for fabricating MEMS structures. Such structures have dimensions on the order of tens of microns. Typical surface micro-machining processing steps are illustrated via
FIGS. 1A-1C
, which depict the fabrication of a simple MEMS structure (i.e. a cantilevered beam).
A first processing step involves forming a layered structure by depositing various layers on a substrate—typically crystalline silicon. The deposited layers usually include alternating layers of: (1) a sacrificial layer, such as silicon dioxide, and (2) a mechanical/structural layer, such as polysilicon or silicon nitride. The number of deposited layers varies as a function of the complexity of the device, etc. For the basic structure shown in
FIG. 1A
, only one sacrificial layer
102
and one mechanical layer
104
are required on substrate
100
.
In a second processing step, either one or both of the sacrificial and mechanical layers are “patterned.” Patterning typically defines the final shape of the mechanical layer(s). In
FIG. 1B
, mechanical layer
104
is patterned wherein a portion of it (i.e., region
106
) is removed via photolithography. Photolithographic steps, which are well-known in the art, involve depositing photoresist on a layer, exposing the photoresist to UV through a mask that defines the pattern that is to be reproduced in the mechanical layer, and then etching to actually form the desired shape or pattern in the mechanical layer.
In a third processing step, the mechanical layer is “released,” wherein it becomes separated, at least in part, from the underlying sacrificial layer. As a consequence of such release, the mechanical layer becomes movable.
FIG. 1C
depicts a released structure, wherein a portion of sacrificial layer
102
is etched away, using, for example, KOH, TMAH, or HF. As a result of etching, cantilevered portion
108
of mechanical layer
104
is formed, wherein gap
112
separates cantilevered portion
108
from substrate
100
. The remaining portion
110
of sacrificial layer
102
supports mechanical layer
104
. See Bustillo et al., “Surface Micro-machine for Microelectromechanical Systems”, Proceedings of IEEE, vol.86, No.8, pp.1552-1574, 1998.
A wide range of MEMS structures have been made using the conventional surface micro-machining method described above. Nevertheless, this process has certain limitations that are due, at least in part, to the use of a sacrificial layer (i.e., the necessity of having to etch the sacrificial layer to release the mechanical layer). Such limitations include:
A limited ability to integrate, on single chip, micro-mechanical devices with semiconductor devices (e.g., CMOS, etc.). In particular, semiconductor devices are usually damaged by sacrificial-layer etchants, so semiconductor devices cannot be fabricated before micro-mechanical devices unless they are protected, such as by the application of photoresist or other materials during fabrication. See U.S. Pat. No. 6,020,272 to Fleming. And released micro-mechanical devices cannot survive the high temperature processing typical for semiconductor-device fabrication, so semiconductor devices cannot be fabricated after micro-mechanical device fabrication. But see, e.g., Biebl et al., “Micromechanics compatible with a 0.8 micro-meter CMOS Process,” Sensors and Actuators A, vol.47, No.1-3, pt.4, pp.593-597, 1995 and Bustillo et al., above.
A limited ability to fabricate micro-mechanical parts from crystalline silicon, which, in many MEMS applications, is preferable to using polysilicon because of its better uniformity and mechanical properties (e.g., relative to single crystal silicon, the granularity of polysilicon results in lower mechanical strength and inferior electronic properties). In the prior art, if crystalline silicon were to be used as the mechanical layer of a MEMS device, a silicon-on-insulator wafer would typically be used. Such silicon-on-insulator wafers are disadvantageously far more expensive than layered structures comprising polysilicon mechanical layers.
A limited area of continuously released mechanical structure. To release a large-area structure, a long lateral etching path is required. But, fresh etchant cannot readily be delivered far from the beginning of a lateral etching path.
The art would therefore benefit from an improved method for fabricating MEMS devices. Such a method would incorporate steps for the release of mechanical layers that avoid the drawbacks of the prior art.
SUMMARY OF THE INVENTION
In some embodiments, a method in accordance with the present invention provides a fabrication method for MEMS devices and hybrid MEMS/semiconductor devices that avoids the drawbacks of the prior art. In particular, in some embodiments, the method includes steps for the release of a structural member without the use of a sacrificial layer.
In some embodiments, a micro-mechanical structure is fabricated by:
forming a buried hydrogen-rich layer in a semiconductor substrate;
defining a release structure in the semiconductor substrate above the buried hydrogen-rich layer;
separating at least a portion of the release structure from the semiconductor substrate by cleaving the semiconductor substrate at the buried hydrogen-rich layer.
The buried hydrogen-rich layer is formed by any one of several methods, including conventional ion implantation. The operation of separating the release structure from the semiconductor substrate is performed by any one of several methods, including thermal treatment, that cause a change in the structure of the buried hydrogen-rich layer. The change, which is believed to involve the conversion of the buried layer into a continuous gaseous layer, results in cleavage of the semiconductor. The semiconductor substrate is advantageously mono-crystalline silicon.
Since the release step proceeds without the use of etchant, the present invention allows, or at least simplifies, the fabrication of “hybrid” devices in which a MEMS structure and a semiconductor device are fabricated in close proximity on the same chip. In particular, in accordance with some embodiments, a hybrid device is fabricated by proceeding with the fabrication of the semiconductor device until high temperature processing steps are complete. Semiconductor processing is thereafter suspended. MEMS fabrication procedures then begin, wherein a release structure is defined and a buried hydrogen-rich layer is formed in the substrate.
The semiconductor device and the MEMS device are then metalized. In particular, electrical contacts are formed for the semiconductor device and elements of the MEMS structure are metalized as appropriate. In some embodiments, metal that is deposited on the nascent release structure functions as a strained layer, a stiffener, and an electrical contact to the semiconductor device. The MEMS release structure is then released by adding energy to the buried hydrogen-rich layer.
In the practice of the present invention, there is no need to protect the semiconductor device (e.g., by applying a protective layer of photoresist that must be later stripped off) as in some prior art methods, since etchant is not used for the release step.
REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5882987 (1999-03-01), Srikrishnan
patent: 6020272 (2000-02-01), Fleming
J. M. Bustillo, R. T. Howe, R. S. Muller, Surface Micromachining for Microelectromechanical Systems, Proceedings of the IEEE, vol. 86, No. 8, (1998), pp. 1552-1574.
M. Biebl, T. Scheiter, C. Hierold, H.v. Philipsborn, H. Klose, Micromechanics Compatible with an 0.8 micrometer CMOS Process, Sensors and Actuators A V. 46-47 (1995) 593-597.
C. H. Yun, A. B.Wengrow, N. W.Cheung, “Transfer of patterned ion-cut silicon layers”, Applied Physi
DeMont & Breyer
Hiteshew Felisa C.
Silicon Wafer Technologies
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