Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
2000-12-18
2002-06-04
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S233100, C365S230020
Reexamination Certificate
active
06400640
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory addressing method and, more particularly, to a memory addressing method in which the column address is input prior to the input of the row address.
2. Description of the Prior Art
Most computer systems use system memories by employing the address multiplexing scheme of inputting the column address subsequent to inputting the row address.
Generally, memories are devices designed to enable the storage and retrieval of data to/from a particular location. Thus, memories are provided with a data bus for data transmission and an address bus for specification of location. As the memory size increases, more addresses are required for specification of location. Accordingly, the number of pins in the memory device has to be increased, thus causing increased manufacturing cost and problems with packaging.
Therefore, from the 64 kilobit generation of memory devices, the address multiplexing scheme has been employed, wherein the cells storing data in the memory device are arranged in two dimensions and the row and column addresses are provided successively. Because in the address multiplexing scheme the row address and the column address are supplied at a different timing, the pins in the memory device can be shared.
The operation of the address multiplexing scheme will be briefly illustrated below.
First, when the row address is supplied, the row path in the two-dimension cell array is first activated so that the data stored in the selected row is read via the sense amplifier. Subsequently, the column path is activated by way of supplying the column address, so that the column data is output.
The row and column addresses are generated by the memory controller in computer systems. When the central processing unit (CPU) requests data stored in a particular address of the memory, the memory controller facilitating communication of data between the CPU and the memory converts the address specified by the CPU to row and column addresses compatible with the memory structure used in the system. In this case, the memory is operated successively by accessing the row path first and then the column path, making this memory addressing scheme very efficient. Most personal computers or workstation systems employ this memory addressing scheme in their system memories, and likewise most memory devices are designed to accommodate this memory addressing scheme.
FIG. 1
is a diagram illustrating the pipeline process of a read operation in a high speed synchronous dynamic random access memory (SDRAM), and
FIG. 2
is a diagram illustrating the pipeline process of a write operation in a high speed SDRAM.
The pipeline process of a read operation will be illustrated with reference to FIG.
1
. When the ROW #1 address signal is input, the row path selected by the ROW #1 address signal is activated. When the COL #1 address signal is input, the column path selected by the COL #1 address signal is activated. At this point, data is transferred from the row path to the column path, and utilizing the transferred data the column path becomes capable of independent operation without the row path. Thus, the row path can receive a new row address to carry out another operation. Therefore, in the read operation, data can be continuously accessed without pipeline stall even if the column address (/CAS) is input subsequent to the input of the row address (/RAS). However, because the order of inputting addresses is fixed in the above addressing scheme, system performance may be deteriorated. This drawback will be illustrated with reference to FIG.
2
.
In a write operation, no data transfer occurs until the column address signal is input, because data is first transmitted from the outside of the memory to the column path in a write operation. When the COL #1 address signal is input as shown in
FIG. 2
, data can be received from the outside of the memory because the column path is activated. At this point, the row path is in the activated state in order to receive data from the column path, and the address input column maintains the stall state because another address signal cannot be input to the address input column. When the row path completes receiving data from the column path, ROW #2 address signal is sequentially input to activate the row path. At this point, the column path maintains the stall state until the COL #2 address signal is input. Thereafter, the above operation is repeated. Thus, in the write operation, pipeline stall occurs repeatedly when the column address (/CAS) is input after the row address (/RAS) is input as in the read operation. This leads directly to increase of memory data access time. That is, unlike a data read operation, in a memory write operation, data from the outside of the memory passes through the column path, and then is stored in the memory cell via the row path. However, in conventional addressing schemes, the column address is input after the row address is input, so that the two operations (read and write) cannot be superimposed. This results in inefficiency.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide, in a memory employing address multiplexing, a memory addressing method capable of increasing memory access speed by merely changing the memory addressing order in the memory read and write operations without change in system structure.
It is another object of the present invention to provide a memory addressing method capable of enhancing the efficiency in the operations of memories.
To this end, a memory addressing method is provided in a system having a memory controller that receives an address requested by a system control unit and converts the received address to a row address and a column address that is compatible with a structure of a connected memory, the memory addressing method comprising the steps of activating a column path by generating the column address when the address is input for data access, and activating a row path by generating the row address according to the address.
REFERENCES:
patent: 5418745 (1995-05-01), Watanabe
patent: 5774402 (1998-06-01), Lee
patent: 5777946 (1998-07-01), Inuzuka et al.
patent: 5978296 (1999-11-01), Zibert
patent: 6191999 (2001-02-01), Fujieda et al.
Woo Ramchan
Yoo Hoi Jun
Yoon Chi Weon
Foley & Lardner
Hoang Huan
Korea Advanced Institute of Science and Technology
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