Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-12-26
2006-12-26
Nguyen, VanThu (Department: 2824)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C375S356000, C713S400000
Reexamination Certificate
active
07154809
ABSTRACT:
A memory buffer for a memory module board which is connected via a signal line (10-i) to a plurality of memory modules (2-i) mounted on said memory module board having different signal line lengths, wherein the memory buffer (1) comprises for each signal line (10-i) a corresponding integration circuit (18-i) for integrating the transmission time of a measurement pulse transmitted via said signal line (10-i) between said memory buffer (1) and a memory module (2-i) connected to said signal line (10-i).
REFERENCES:
patent: 5852640 (1998-12-01), Kliza et al.
patent: 6456544 (2002-09-01), Zumkehr
patent: 6724685 (2004-04-01), Braun et al.
patent: 2003/0014680 (2003-01-01), Zielbauer
Gregorius Peter
Lindt Paul Georg
Mattes Heinz Ludwig
Infineon - Technologies AG
Jenkins Wilson Taylor & Hunt, P.A.
Nguyen Van-Thu
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