Data processing: measuring – calibrating – or testing – Measurement system in a specific environment – Quality evaluation
Reexamination Certificate
2001-01-08
2004-03-30
Barlow, John (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system in a specific environment
Quality evaluation
Reexamination Certificate
active
06714885
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method for measuring an accurate value of yield loss due to chip defect caused by the inflow of dust or foreign material or due to poor shapes of chips during semiconductor manufacturing processes.
BACKGROUND ART
Defects of wafer chips caused by dust, foreign material, and poor shapes of the chips during semiconductor manufacturing processes critically affect the yield and characteristics of chips. Such a defect is generated in all handling processes including environment as well as all equipments and all semiconductor manufacturing processes. Thus, this makes the range of management of defects required by field managers very broad. Accordingly, production and quality management of chips is difficult.
Defects of chips critically affect the yield loss and characteristics of the chips. The yield loss is generally 1 through 30% of defective chips. Namely, the degree of yield loss varies according to processes with respect to the same numbers of defective chips. The degree of the yield loss varies according to products. The degree of the yield loss varies according to the degree and type of defects.
For example, in the case of a dynamic random access memory (DRAM), a poor chip is obtained when a defect exists outside a memory cell region. However, when a defect exists inside the memory cell region, a good chip can be obtained by performing a laser repair using a redundancy cell. Namely, the degree of yield loss varies in the same chip according to the positions of the defect.
Since the causes of yield loss during the fabrication of the semiconductor chips are derived from all processes such as a photolithography process, an etching process, a diffusion process, an ion implantation process, and a thin film deposition process as well as the above defects, it is difficult to determine how much effect defects have on yield loss.
It is difficult to manage yield by managing defects since the degree of yield loss varies according to products when defects are generated, the degree of the yield loss varies according to processes with respect to the same product, and defects are generated in all processes, equipments, circumstances, and handling processes of a semiconductor fabrication field.
It is possible to measure the total number of defects generated on a wafer, the total number of defective chips by the degree and type of defects with current technology of measuring yield loss and characteristics of the chip according to the defects. It is possible to analyze and measure the amount of yield loss to the total number of defects, the number of specific poor chips to the total number of defects, the yield loss amount to the total number of defective chips, and the number of specific poor chips to the total number of defective chips by matching the measurement result to the yield measurement result and statistically processing the result.
Accordingly, when the total number of defects or the total number of defective chips increases, the yield loss amount and specific defect ratio also increase. Namely, it is possible to relatively measure the amount of yield loss to the total number of defects, the number of specific poor chips to the total number of defects, the yield loss amount to the total number of defective chips, and the number of specific poor chips to the total number of defective chips.
As mentioned above, since the causes of yield loss exist in all processes, it is not possible to measure the absolute value of the yield loss by which it is possible to determine how much the chips in which the yield loss occurs are affected by the defect.
DISCLOSURE OF THE INVENTION
It is a first object of the present invention to provide a method for measuring the number of yield loss chips and the number of poor chips by type due to the defects of semiconductor chips by which it is possible to remarkably improve the yield of semiconductor chips by accurately obtaining the number of the yield loss chips due to defects of the chips, the maximum number of yield loss chips, and the number of specific types of poor chips in an arbitrary process, an arbitrary equipment, and an arbitrary process section among semiconductor fabrication processes, thus managing the defects of the chips.
It is a second object of the present invention to provide a computer readable medium on which the above method realized as a program is recorded.
Accordingly, to achieve the first object, there is provided a method for measuring the number of yield loss chips and the number of poor chips by type due to defects of semiconductor chips, comprising the steps of checking defective chips among effective chips on a wafer which underwent a predetermined process using a defect examination equipment and plotting the checked defective chips on a first wafer map, forming disparity chips by pairing defective chips and non-defective chips adjacent to the defective chips on the first wafer map and determining a maximum reliability region formed of regions in which the disparity chips are located, plotting good chips and poor chips by type on a second wafer map using a yield measuring apparatus after completing the process, and classifying the number of good chips and poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map.
Accordingly, to achieve the second object, there is provided a computer readable medium including program commands for measuring the number of the yield loss chips and the number of poor chips by type due to the defect of semiconductor chips, the computer readable medium comprising a computer readable code for inputting data on defective chips and non-defective chips among effective chips on a wafer which underwent a predetermined process from a defect examination equipment and plotting the input data on the defective chips and the non-defective chips on a first wafer map, a computer readable code for forming disparity chips by pairing the defective chips and the non-defective chips adjacent to the defective chips on the first wafer map and determining the maximum reliability region comprised of regions in which the disparity chips are located, a computer readable code for inputting data on good chips and poor chips by type from a yield measuring apparatus and plotting the input data on the good chips and the poor chips on a second wafer map, and a computer readable code for classifying the number of the good chips and the poor chips by type on the second wafer map corresponding to the defective chips and the non-defective chips in the maximum reliability region on the first wafer map and mapping out the statistics with respect to the yield loss and the number of the poor chips by type.
REFERENCES:
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patent: 06-310581 (1994-11-01), None
Evans, W. et al., “Partitioning Yield Loss via Test Pattern Structures and Critical Areas”,IEEE/SEMI Advanced Semiconductor Manufacturing Conference, cat. No. 95CH35811, 1995, pp. 167-169,IEEE, New York, NY, USA.
Hansen, C. K., et al., “Use of Wafer Maps in Integrated Circuit Manufacturing”,Microelectronics Reliability, Jun. 1998, pp. 1155-1164, vol. 38, No. 6-8, Elsevier Science Ltd.
Mill-Jer, W., et al, “Yield Improvement by Test Error Cancellation”,IEEE Proceeding of the Fifth Asian Test Symposium, cat. No. 96BT100072, 1996, pp. 258-262,IEEE, Los Alamitos, CA, USA.
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Barlow John
Isemicon, Inc.
Lau Tung
Rothwell Figg Ernst & Manbeck
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