Method for measuring latencies by randomly selected sampling of

Electrical computers and digital processing systems: processing – Architecture based instruction processing

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712202, 712216, 395709, G06F 500

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active

060921803

ABSTRACT:
In a method for scheduling instructions executed in a computer system including a processor and a memory subsystem, pipeline latencies and resource utilization are measured by sampling hardware while the instructions are executing. The instructions are then scheduled according to the measured latencies and resource utilizations using an instruction scheduler.

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