Method for measuring gate length and drain/source gate overlap

Details Method for measuring gate length and drain/source gate overlap Method for measuring gate length and drain/source gate overlap

1999-01-26

2000-12-26

Nguyen, Vinh P.

Electricity: measuring and testing

Fault detecting in electric circuits and of electric components

Of individual circuit component or element

H01L 2978

Patent

active

061665584

ABSTRACT:
The invention provides a method and apparatus for calculating gate length and source/drain gate overlap, by measuring gate capacitance. The invention uses previously known fringe capacitance C.sub.fr and unit capacitance C.sub.OX. The invention measures gate capacitance C.sub.g, when the gate is accumulatively biased, and solves for overlap capacitance C.sub.OV using the equation C.sub.OV =(C.sub.g -2C.sub.fr)/2 or C.sub.OV =(C.sub.gg -C.sub.gb -2C.sub.fr)/2. The invention then measures the gate capacitance C.sub.g when the gate to source/drain voltage is set to inversion bias and a zero voltage is applied between the source/drain and the substrate, and solves for the channel capacitance C.sub.ch using the equation C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV. The invention calculates the channel capacitance C.sub.ch where C.sub.ch =C.sub.g -2C.sub.fr -2C.sub.OV and then calculates gate length where gate length L.sub.g =(2C.sub.OV +C.sub.ch)/C.sub.OX and the effective gate length L.sub.eff =C.sub.ch /C.sub.OX. The invention further calculates source/drain gate overlap L.sub.OV, by setting L.sub.OV =C.sub.OV /C.sub.OX.

REFERENCES:
patent: 5194923 (1993-03-01), Vinal
patent: 5268318 (1993-12-01), Harari
patent: 5600578 (1997-02-01), Fang et al.
U.S. application No. 09/237,539, Wei Long, Yowjuang W. Liu, Chun Jiang., filed Jan. 26, 1999.
On the Accuracy of Channel Length Characterization of LDD MOSFET's Jack Y. -C. Sun, Matthew R. Wordeman, Stephen E. Laux, 1986, 7 pages (month unavailable).
An Accurate Gate Length Extraction Method for Sub-Quarter Micron MOSFET's, Cheng-Liang Huang, John V. Faricelli, Dimitri A. Antoniadis, Nadim A. Khalil, Rafael A. Rios, 1996, 6 pages (month unavailable).
A Problem-Specific Inverse Method for Two-Dimesional Doping Profile Determination from Capacitance-Voltage Measurements, G. J. L. Ouwerling, 1991, 18 pages (month unavailable).
The Extraction of Two-Dimensional MOS Transistor Doping via Inverse Modeling, Nadim Khalil, John Faricelli, David Bell, Siegfried Selberherr, 1995, 3 pages (month unavailable).
A New "Shift and Ratio" Method for MOSFET Channel-Length Extraction, Yuan Taur, D.S. Zicherman, D.R. Lombardi, Phillip J. Restle, C.H. Hsu, Hussein I. Hanafi, Matthew R. Wordeman,Bijan Davari, Ghavam G. Shahidi, 1992, 3 pages.
CMOS Circuit Design, Layout, and Simulation, R. Jacob Baker, Harry W. Li, David E. Boyce, 1997, 5 pages (month unavailable).
A New Capacitance Measurement Method for Lateral Diffusion Profiles in Mosfet's with Extremely Short Overlap Regions, H. Uchida, Y. Kajita, K. Fukada, J. Ida, N. Hirashita, K. Nishi, publication date unknown, 2 pages (month unavailable).

Affiliated with

Also associated with

Rating

Method for measuring gate length and drain/source gate overlap does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for measuring gate length and drain/source gate overlap, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for measuring gate length and drain/source gate overlap will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-999055