Method for mathematically processing two quantities in an...

Details Method for mathematically processing two quantities in an... Method for mathematically processing two quantities in an...

2000-07-31

2003-06-24

Mai, Tan V. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical analog calculating computer

Particular function performed

C708S801000

Reexamination Certificate

active

06584486

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
This application claims the priority of Swiss patent application 1448/99, filed Aug. 6, 1999, the disclosure of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
The invention relates a method for mathematically processing two quantities in an electronic circuit.
Analog addition circuits are usually based on the principle of current addition. Such adders are not always suitable for implementation in integrated circuits.
BRIEF SUMMARY OF THE INVENTION
Hence, it is a general object of the invention to provide a method of this type that is suited for integration.
Now, in order to implement these and still further objects of the invention, which will become more readily apparent as the description proceeds, the method for mathematically processing at least two values r
x
and r
y
in a combination circuit uses a combination circuit comprising two current inputs E
x,0
and E
x,1
for the value r
x
, two voltage inputs E
y,0
and E
y,1
for the value r
y
, two current outputs A
0
and A
1
for a result r
z
, and four transistors T
0,0
, T
0,1
, T
1,0
, T
1,1
, wherein the sources or emitters of the transistors T
0,0
and T
0,1
are connected to the current input E
x,0
, the sources or emitters of the transistors T
1,0
and T
1,1
to the current input E
x,1
, the gates or bases of the transistors T
0,0
and T
1,0
to the voltage input E
y,0
, the gates or bases of the transistors T
0,1
and T
1,1
to the voltage input E
y,1
, the drain or collector of the transistor T
0,0
to the current output A
0
, the drain or collector of the transistor T
1,1
with the current output A
1
, and the drains or collectors of the transistors T
0,1
and T
1,0
to a reference potential providing a saturation or forward polarization. The method comprises the steps of
feeding two input currents I
x
p
x
(
0
) and I
x
p
x
(
1
) through the current inputs E
x,0
and E
x,1
, wherein a quotient of said input currents is equal to e
r
x
,
applying an input voltage between said voltage inputs E
y,0
and E
y,1
proportional to r
y
, and
generating, with said combination circuit, two output currents at the current outputs A
0
and A
1
, wherein a quotient of said output currents is equal to e
r
x
+r
y
, and
deriving, from said output currents, a sum of the values r
x
and r
y
.
The method relies on a circuit consisting of transistors only. Every quantity is represented by a pair of currents or by a voltage between two voltage input terminals. If some quantity r is represented by a pair of currents, the ratio of the two currents corresponds to e
r
; if it is represented by a voltage, the voltage corresponds to r. Transformations between these two representations can also be realized by simple circuits that consist of transistors only and can be integrated easily.
In references H. -A. Loeliger, F. Lustenberger, M. Helfenstein, F. Tarköy, “Probability Propagation and Decoding in Analog VLSI”, Proc. of 1998 IEEE Intl. Symposium on Information Theory, Cambridge, Mass., 16-21 August 1998, p. 146 referred to as [1]), in F. Lustenberger, M. Helfenstein, H. -A. Loeliger, F. Tarköy, and G. S. Moschytz, “An Analog Decoding Technique for Digital Codes”, Proceedings of ISCAS '99, Orlando, Fla., May 30-Jun. 2, 1999, vol. II, pp. 428-431 (referred to as [2]), as well as in H. -A. Loeliger, F. Tarköy, F. Lustenberger, M. Helfenstein, “Decoding in Analog VLSI”, IEEE Communications Magazine, vol. 37, no. 4, April 1999, pp. 99-101 (referred to as [3]), a type of transistor network was presented by which a variety of signal processing algorithms—in particular the decoding of error correcting codes—can be realized. These analog networks work with quantities that represent probabilities. The invention presented here expands the application of such networks to tasks that, at first sight, have nothing to do with probabilities. In particular, one circuit of [1] is now used as an adder. With such adders, a number of signal processing algorithms such as, for example, discrete-time adaptive analog filters can be realized as circuits with advantageous properties. In particular, networks containing both such adders and Gilbert-multipliers are suitable for preprocessing data that is subsequently processed by the probability networks presented in [1].
The claimed method can be.applied in a variety of ways, e.g. in correlators and filters.


REFERENCES:
patent: 4374335 (1983-02-01), Fukahori et al.
patent: 4586155 (1986-04-01), Gilbert
patent: 5389840 (1995-02-01), Dow
patent: 5764559 (1998-06-01), Kimura
patent: 6014685 (2000-01-01), Marshall et al.
patent: 19725275 (1998-12-01), None
patent: 1024450 (2000-08-01), None
1998 IEEE ISIT, Aug. 16-21, 1998, p. 146, Hans-Andrea Loeliger et al., “Probability Propagation and Decoding in Analog VLSI”.
1999 IEEE-ISCAS '99, May 30-Jun. 2, 1999, pp II-424-1427, Felix Lustenberger et al., “An Analog VLSI Decoding Technique for Digital Codes”.
IEEE Communications Magazine, Apr. 1999, vol. 37, No. 4, pp 99-101, Hans-Andrea Loeliger et al., “Decoding in Analog VLSI”.
IEEE Journal of Solid-State Circuits, vol.-SC-3, No. 4, Dec. 1968, pp. 365-373, Barrie Gilbert, “A Precise Four-Quadrant Multiplier with Subnanosecond Response”.
IEEE Journal of Solid-State Circuits, vol. SC-19, No. 6. Dec. 1984, pp 956-963, Barrie Gilbert, “A Monolithic 16-Channel Analog Array Normalizer”.
IEEE Circuits and Systems Series 5, Chapter 3, pp 31-70, John B. Hughes et al., “Switched-Current Architectures and Algorithms”, Undated.
IEEE Transactions on Communications, vol. 36, No. 1, Jan. 1988, pp 13-20, M. Vedat Eyubo{haeck over (g)}lu et al., “Reduced-State Sequence Estimation with Set Partitioning and Decision Feedback”.

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