Method for masking false bound faults in a central processing un

Details Method for masking false bound faults in a central processing un Method for masking false bound faults in a central processing un

1990-02-21

1992-08-11

Smith, Jerry

Excavating

G06F 1100

Patent

active

051386178

ABSTRACT:
In a computer system having a hardware and/or firmware design problem which causes a false boundary error under certain conditions, the subject method serves to handle and correct the false boundary error condition in the operating system. This recovery process is carried out such that the information from which the faulting address was developed is redistributed among a plurality of information components in such a manner that the false boundary error will not recur on retry. Thus, the process masks the problem by remapping the virtual address components of the faulting instruction so that the final virtual address, though identical to the failing one, is processed without fault by the central processor unit during recovery.

REFERENCES:
patent: 4025771 (1977-05-01), Lynch, Jr. et al.
patent: 4437149 (1984-03-01), Pomerene et al.
patent: 4456996 (1984-06-01), Haas et al.
patent: 4641305 (1987-02-01), Joyce et al.
patent: 4646298 (1987-02-01), Laws et al.
patent: 4922491 (1990-05-01), Coale
patent: 4967387 (1990-10-01), Shibasaki et al.

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