Classifying – separating – and assorting solids – Sorting special items – and certain methods and apparatus for... – Condition responsive means controls separating means
Reexamination Certificate
2001-10-22
2004-01-06
Noland, Kenneth W. (Department: 3653)
Classifying, separating, and assorting solids
Sorting special items, and certain methods and apparatus for...
Condition responsive means controls separating means
C324S1540PB
Reexamination Certificate
active
06674036
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to packaged integrated circuits (ICs). More particularly, the invention relates to a method for marking packaged ICs.
BACKGROUND OF THE INVENTION
ICs are normally “packaged” prior to sale, e.g., mounted in plastic or ceramic carriers that protect the IC. The IC package is then typically mounted on a circuit board, while “package pins” incorporated in the package allow electrical contact (through fragile internal “bond wires”) between the pads of the IC and traces on the board. Commonly used packages include dual in-line (DIP) packages, ball grid arrays (BGA), and many other well-known packages.
Because many different ICs are generally available in a given package, packaged ICs are normally marked with both product tracking information and product identity information prior to sale. The product tracking information typically includes the wafer fabrication lot number and the date on which the wafer was fabricated, as well as the assembly lot number and the date on which the packaged IC was assembled. This information allows the manufacturer to track the manufacturing process and assists in solving manufacturing problems. Product identity information typically includes designations for the product type, package type, and performance (speed grade) of the IC.
FIG. 1
shows a common package marking flow. Typically, an IC device is tested briefly while still on the wafer (step
100
). ICs failing the tests are discarded (step
102
). ICs passing the tests are packaged (step
104
), then marked on the back with product tracking information (step
106
). After this step, the packaged IC looks as shown in
FIGS. 1A
(bottom view) and
1
B (top view).
After the ink on the bottom of the package has cured, the package is marked on the front (step
108
) with additional information intended for the customer, typically product identity information. Product tracking information may also be included. For example, as in
FIG. 1C
, a marked IC may display the company name and logo, an alphanumeric string including the product identity information (PRODUCTIDENTITY), and one or more strings including the product tracking information (PRODUCTTRACKING).
FIG. 1D
shows the marked information in more detail. The IC of
FIG. 1D
displays the product identity information in the form of a product designator (Prod), package identifier (pkg), and speed grade (spd-grade). Product tracking information includes the wafer lot, processing date, assembly lot, and assembly date.
Because the actual performance of the device is not known at this time, the highest specified performance is typically included on the front markings. Alternatively, the speed grade can be omitted from the markings, and added later after the performance has been determined.
The marked packaged IC is then subjected to further tests (step
110
) to determine full functionality and performance. ICs failing the tests are discarded (step
112
). If a speed grade was marked on the IC in step
108
, then the ICs are tested against the marked speed grade. Otherwise functional ICs in any lower speed grade will fail the tests and must then be discarded. If no speed grade was marked on the IC in step
108
, the actual, measured performance can be marked on the IC in a third marking step (not shown). Because marking is a slow and expensive process, it is common for IC manufacturers to simply mark the fastest speed grade and accept the losses of discarding slower ICs, for at least a portion of their output.
The fully tested and marked ICs are then stored until a customer order is received (step
114
), at which time an IC is selected and shipped to the customer (step
116
).
This straightforward process has several deficiencies. If each package is marked with the highest specified speed grade in step
108
, some slower devices must be unnecessarily discarded. If the speed grade is not marked until later in the process, a total of three marking steps must be performed. Even in this case, the fabrication, testing, and marking process may result in a distribution of ICs that does not correspond to the distribution desired by customers. For example, a fast IC is typically more expensive than a corresponding slow IC. Therefore, customers who do not need fast ICs are not willing to pay a premium for them, yet the fabrication, testing, and marking process may result in a large number of ICs marked “fast” and a small number of ICs marked “slow”. In this case, it is common industry practice to sell a fast IC at the price of a slow IC, and in these circumstances it is desirable to mark the IC package with the speed grade for which the customer paid, not the speed grade at which the packaged IC functioned when tested. Further, customers sometimes wish to purchase unusual combinations of, for example, speed grades and temperature ranges, or even to purchase speed grades or temperature ranges not normally tested for. In this case, a manufacturer can easily test the product to the customer's specifications. However, the product has already been marked in a fashion that may not be consistent with the customer's needs. Therefore, it is not uncommon for a manufacturer to deliberately remove product identity markings and replace them with new product identity markings.
The marking removal process typically involves sanding, sandblasting, a covering of paint, or laser ablation, and can for some inexpensive ICs cost more than the IC itself. Further, the physical handling of the package necessary to remove the markings can cause damage to the fragile bond wires within the package. In fact, in the case of thin packages, the potential damage is such that some of these processes cannot be used.
In addition, sanding and sandblasting mar the finish of the package, which may be unacceptable to the customer. Painting the package is sometimes messy, and often does not fully hide the previous mark due to a textural difference between the bare package and the raised surface of the marking. This overcoat can also fail over time to adhere to the package, or can be found cosmetically unacceptable to the customer. Laser removal also mars the finish of the package and may be cosmetically unacceptable.
In order to avoid the potentially expensive and damaging step of removing product identity markings, one known marking method delays adding the product identity markings until after determining the customer's needs. This process is illustrated in FIG.
2
. The product tracking information is marked on the back of the packaged IC as in
FIG. 1
(step
106
). The product identity information is not marked on the package at this time. The packaged IC is then tested (step
208
) to determine the actual tested performance of the IC. Any IC not meeting a minimum specified performance, or not passing the functional tests, is discarded. The IC is then “binned”(i.e., stored, typically in a marked bin) according to the actual performance of the IC (step
212
). The partially marked packaged IC is held until a customer order is received (step
214
) and a suitable IC is selected (step
216
). A suitable IC may be an IC either meeting or exceeding the customer's performance requirements. In some cases, especially where the customer has non-standard requirements, additional testing is performed at this point in the process to verify the suitability of the selected device. The product identity information appropriate to the sale is then marked on the top side of the selected packaged IC (step
218
) and the IC is delivered to the customer (step
220
).
In a variation on the method of
FIG. 2
, after step
106
, all product identity information except for the speed grade is marked on the front of the package. The packaged IC is the tested as in step
208
of
FIG. 2
, and the passing ICs are binned as in step
212
. The partially marked packaged IC is held until a customer order is received (as in step
214
) and a suitable IC is selected (as in step
216
). The speed grade appropriate to the sale is then added to the markings on the top
Cartier Lois D.
Noland Kenneth W.
Xilinx , Inc.
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