Method for manufacturing VLSI MOS-transistor circuits

Details Method for manufacturing VLSI MOS-transistor circuits Method for manufacturing VLSI MOS-transistor circuits

1985-10-02

1987-04-21

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29576B, 29578, 148 15, 148187, 148DIG82, 148DIG140, 156643, 357 42, 357 91, H01L 21265, H01L 21308

Patent

active

046584960

ABSTRACT:
A method for manufacturing VLSI MOS-transistor circuits involving the production of transistors by means of a spacer layer technique and ohmic contacts from the gate interconnect to the diffused regions of the substrate (thus providing buried contacts) both being simultaneously generated. Contact holes are provided at the desired location in the substrate before the deposition of the spacer layer occurs across the surface of the substrate. The spacer layer is simultaneously structured at the side walls of the gates and at the side walls of the interconnects which serve as connections. The contact hole region is doped at the same time as the source/drain areas are provided by ion implantation. The combined manufacture of transistors using spacer technology and buried contacts makes it possible to manufacture MOS logic circuits and memory circuits with voltage stable transistors in high packing density.

REFERENCES:
patent: 3699646 (1972-10-01), Vadasz
patent: 4356623 (1982-11-01), Hunter
patent: 4366613 (1983-01-01), Ogura et al.
patent: 4478679 (1984-10-01), Chang et al.
patent: 4488351 (1984-12-01), Momose
patent: 4536944 (1985-08-01), Bracco et al.
patent: 4566175 (1986-01-01), Smayling et al.
patent: 4569122 (1986-02-01), Chan
patent: 4577391 (1986-03-01), Hsia et al.
Murarka et al. IEEE-Jour. Solid St. Circuits, SC-15 (1980) 474.
Tsang et al., "Fabrication of High-Performance LDDFET'S With Oxide Sidwall-Spacer Technology, Citations IEEE Transactions, Apr. 1982.
Miyamoto et al., "A. 1.0um N-Well CMOS/ Bipolar Technology for VLSI Circuits", IEDM, vol. 83, pp. 63-66.
Dash et al., IBM Technical Disclosure Bulletin, vol. 24, No. 6 (Nov. 1981), p. 2863.

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