Method for manufacturing VLSI complementary MOS field effect tra

Details Method for manufacturing VLSI complementary MOS field effect tra Method for manufacturing VLSI complementary MOS field effect tra

1982-08-09

1984-07-17

Roy, Upendra

Metal working

Method of mechanical manufacture

Assembling or joining

29571, 148 15, 148187, 357 42, 357 91, H01L 2122, H01L 2978, H01L 21265

Patent

active

044597401

ABSTRACT:
Complementary MOS field effect transistor circuits are produced in silicon gate technology, with the method steps up to the structuring of the gate electrode being executed in a known manner. Both source/drain implantations (FIG. 3, 8 and FIG. 5, 10) occur with only one mask (7a). This mask (7a), which is composed of silicon nitride, is utilized for the source/drain implantation 8 of the n-channel transistors (9). The source/drain implantation (10) for the p-channel transistors (11) occurs without a mask and the oxide layer thickness, d.sub.6, over the source/drain regions of the n-channel transistors (9) functions as a masking layer. An advantage of this process sequence is that switched capacitor structures (FIG. 6, 5b, 12) can be simultaneously produced whereby the oxide layer thickness, d.sub.4, over the polysilicon-1 level (5a, 5b) determines the thickness of the insulating layer, d.sub.cox, of the capacitor structures (5b, 12). This technique is useful for manufacturing VLSI CMOS circuits in VLSI technology with and without switched capacitors.

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T. Ohzone et al., "Silicon-Gate n-Well CMOS Process by Full Ion-Implantation Technology", IEEE Transactions on Election Devices, vol. ED-27, (1980), pp. 1789-1795.
L. C. Parrillo et al., "Twin-Tub CMOS-A Technology for VLSI Circuits", IEDM Technical Digest, (1980), Paper 29.1, pp. 752-755.

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