Method for manufacturing VLSI complementary MOS field effect cir

Details Method for manufacturing VLSI complementary MOS field effect cir Method for manufacturing VLSI complementary MOS field effect cir

1984-06-05

1985-06-25

Pianalto, Bernard D.

Coating processes

Electrical product produced

Integrated circuit, printed circuit, or circuit board

427 431, 427 85, 427 93, 427 94, 427 96, 427259, 427265, B05D 306

Patent

active

045253781

ABSTRACT:
A method for manufacturing VLSI complementary MOS field effect transistor circuits (CMOS circuits). By use of a suitable gate material, preferably a gate material comprised of silicides of high melting point metals, a threshold voltage of n-channel and p-channel CMOS-FETs having gate oxide thicknesses d.sub.GOX in a range of 10 to 30 nm is simultaneously symmetrically set by means of a single channel ion implantation. Given employment of tantalum silicide, the gate oxide thickness d.sub.GOX is set to 20 nm and the channel implantation is executed with a boron dosage of 3.times.10.sup.11 cm.sup.-2 and an energy of 25 keV. In addition to achieving a high low-level break down voltage for short channel lengths, this enables the elimination of a photolithographic mask. This represents an improvement with respect to yield and costs. The method serves for the manufacture of analog and digital CMOS circuits in VLSI technology.

REFERENCES:
Article by L. C. Parillo et al. in the Technical Digest IEDM, 1980, vol. 29.1, pp. 752-755 "Twin-Type CMOS-Technology for VLSI Circuits".
"High Packing Density High Speed CMOS Device Technology" by Sakai et al., Japanese Journal of Applied Physics, vol. 18, Supplement 18-1, pp. 73-78.

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