Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-07-28
2001-10-16
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S426000, C257S506000
Reexamination Certificate
active
06303467
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor manufacturing, and more particularly to a method for manufacturing trench isolation for isolating each element from one another in semiconductor substrate, which can be useful in sub-micron semiconductor manufacturing.
2. Description of the Prior Art
Due to the development of ULSI manufacturing technology, semiconductor manufacturing is improved into the technical level of fabricating integrated circuits with relatively high density. To prevent that semiconductor elements interfere from each other, it is necessary to fabricating effective isolating regions between semiconductor elements, to avoid short circuit among them. However, when semiconductor elements increasingly shrink, the density of integrated circuits is increased, and it is more difficult to fabricating effective and reliable isolation regions to isolate active areas from each other in which semiconductor elements is constituted. It encounters many problems to use the conventional Local Oxidation (LOCOS) method as the isolating regions, such as the formation of bird's beak structure. The bird's beak shape causes unacceptably large encroachment of the field oxide into the active areas. In addition, the planarity of the surface topography attributed to LOCOS is inadequate for sub-micron lithography needs.
Therefore, it is more common to employ trench isolation method such as shallow trench isolation as replacement of LOCOS method, to form trench isolations, which are coplanar with the active areas in the substrate. Typically, a trench is formed by proceeding anisotropically etching in the substrate, depositing a dielectric layer in the substrate to fill it into the trench as isolating material therein, and then planarizing the surface of the dielectric layer by CMP method. Thus, the trench isolations coplanar with adjacent active areas are formed.
Nevertheless, as shown in
FIG. 1
, the trench isolation method provides “corner effect”, that is, there is a sharp corner
1
formed in the crossing region between the trench isolation and the active area. Since after the sequential gate polysilicon layer deposition, the polyslicon layer etching can not attend to the sharp corner. Therefore, it is readily easy to leave polysilicon residue in the sharp corner, and result in short circuit between polysilicon gates.
Accordingly, it is obvious that the conventional method for forming trench isolations is defective and then a mendable method is required, especially in the application of sub-micron semiconductor manufacturing.
SUMMARY OF THE INVENTION
The primary object of the present invention is to provide a method for manufacturing trench isolation, which can smooth a sharp corner in the crossing region between a trench isolation and an active area adjacent thereto in the substrate. Thereby, the polysilicon residue in the corner is eliminated, and short circuit between polysilicon gates is avoided.
Another object of the present invention is to provide a method for manufacturing trench isolation, which can smooth a sharp corner between a trench isolation and an active area adjacent thereto in the substrate, then facilitate sequential deposition and etching of a gate polysilicon layer. Therefore, the process window for the gate polysilicon layer etching is improved.
In order to achieve previous objects of the invention, the present invention provides a method for manufacturing trench isolation, which comprises: providing a substrate; forming a first dielectric material layer over the substrate. Then, defining an isolation region over the substrate by photolithography and etching technique. After that, forming an isolating layer over the substrate having the isolation region, and proceeding anistropically etching to form a spacer around each of the two sides of the isolation region. Then, forming a pad oxide layer over the substrate having the isolation region with spacers formed around. Thereafter, forming a silicon nitride layer over the pad oxide layer. Subsequently, covering a mask over the silicon nitride layer, and performing anisotropically etching in the isolation region to form a trench isolation. Further, forming a second dielectric material layer over the whole substrate to fill the second dielectric material into the trench isolation as isolating material therein; planarizing the second dielectric material layer by chemical mechanical polishing (CMP) method. Finally, removing the pad oxide layer and the silicon nitride layer. A trench isolation with a smooth corner in the crossing region between the trench isolation and an active area adjacent thereto is attained.
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Hung Ya-Ling
Jen Yi-Min
Lu Tse-Yi
Tsao Li-Wu
Blum David S
Bowers Charles
United Microelectronics Corp.
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