Boots – shoes – and leggings
Patent
1995-02-07
1996-07-23
Teska, Kevin J.
Boots, shoes, and leggings
364488, 364578, 36446803, 36446815, 364491, G06F 9455, H01L 2170
Patent
active
055396526
ABSTRACT:
A manufacturing and test simulation method for electronic circuit design integrated with computer aided design tools to provide concurrent engineering of manufacturing and testability aspects of a product concurrent with the functional design of a product. The manufacturing and test simulator (MTSIM) simulates manufacturing test and repair aspects of boards and multichip modules (MCMs) from design concept through manufacturing release to aid the designer in selecting appropriate trade-offs in the design for manufacturability and the design for testability. All simulation by the methods of the present invention applies manufacturing and test models down to the component level. The methods of the simulator include a new yield model for boards and MCMs which accounts for the clustering of solder defects. MTSIM models solder faults, manufacturing workmanship faults, component performance faults, and reliability faults. Fault probabilities for the circuit design are estimated based on the component type, the component functionality, and the assembly process used. Up to seven manufacturing test steps can be simulated by MTSIM. Test coverage models will support all commonly used manufacturing test methodologies, including visual inspection, in-circuit test, IEEE 1149.1 boundary scan, selftest, diagnostics, and burn-in. Pareto and iterative "what-if" analysis may be used to locate particular enhancements which most benefit the manufacturability and testability of the product.
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Josephson D. D., Dixon
Frejd Russell W.
Hewlett--Packard Company
Teska Kevin J.
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