Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – On insulating substrate or layer
Reexamination Certificate
2009-09-23
2011-11-01
Nhu, David (Department: 2895)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
On insulating substrate or layer
C438S692000, C438S663000, C438S706000, C438S745000, C257SE21042, C257SE21043, C257SE21077, C257SE21170, C257SE21320, C257SE21134, C257SE21229, C257SE21304, C257SE21267, C257SE21327, C257SE21328, C257SE21329, C257SE21332
Reexamination Certificate
active
08048754
ABSTRACT:
An object is to provide a single crystal semiconductor layer with extremely favorable characteristics without performing CMP treatment or heat treatment at high temperature. Further, an object is to provide a semiconductor substrate (or an SOI substrate) having the above single crystal semiconductor layer. A first single crystal semiconductor layer is formed by a vapor-phase epitaxial growth method on a surface of a second single crystal semiconductor layer over a substrate; the first single crystal semiconductor layer and a base substrate are bonded to each other with an insulating layer interposed therebetween; and the first single crystal semiconductor layer and the second single crystal semiconductor layer are separated from each other at an interface therebetween so as to provide the first single crystal semiconductor layer over the base substrate with the insulating layer interposed therebetween. Thus, an SOI substrate can be manufactured.
REFERENCES:
patent: 5374564 (1994-12-01), Bruel
patent: 5869387 (1999-02-01), Sato et al.
patent: 6121117 (2000-09-01), Sato et al.
patent: 6251754 (2001-06-01), Ohshima et al.
patent: 6335231 (2002-01-01), Yamazaki et al.
patent: 6534380 (2003-03-01), Yamauchi et al.
patent: RE39484 (2007-02-01), Bruel
patent: 7781308 (2010-08-01), Isaka et al.
patent: 7790563 (2010-09-01), Kakehata
patent: 2009/0042362 (2009-02-01), Moriwaka
patent: 2009/0142904 (2009-06-01), Isaka et al.
patent: 2009/0197392 (2009-08-01), Isaka et al.
patent: 2010/0129948 (2010-05-01), Isaka et al.
patent: 0 553 852 (1993-08-01), None
patent: 1 043 768 (2000-10-01), None
patent: 1 251 556 (2002-10-01), None
patent: 05-211128 (1993-08-01), None
patent: 05-217821 (1993-08-01), None
patent: 09-260619 (1997-10-01), None
patent: 10-093122 (1998-04-01), None
patent: 10-321548 (1998-12-01), None
patent: 11-097379 (1999-04-01), None
patent: 2000-030993 (2000-01-01), None
patent: 2003-017671 (2003-01-01), None
Dross et al., “Stress-Induced Lift-Off Method for Kerf-Loss-Free Wafering of Ultra-Thin (˜50μm) Crystalline Si Wafers,” Proceeding of 33rdIEEE PVSC, 2008, 5 pages.
Hirose Takashi
Isaka Fumito
Kato Sho
Shimomura Akihisa
Nhu David
Robinson Eric J.
Robinson Intellectual Property Law Office P.C.
Semiconductor Energy Laboratory Co,. Ltd.
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