Method for manufacturing SOI substrate

Details Method for manufacturing SOI substrate Method for manufacturing SOI substrate

2008-03-25

2009-11-10

Nhu, David (Department: 2895)

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

On insulating substrate or layer

C438S475000, C438S510000, C257SE21054, C257SE21218, C257SE21227, C257SE21248, C257SE21304

Reexamination Certificate

active

07615456

ABSTRACT:
A method for manufacturing an SOI substrate superior in film thickness uniformity and resistivity uniformity in a substrate surface of a silicon layer having a film thickness reduced by an etch-back method is provided. After B ions is implanted into a front surface of a single-crystal Si substrate10to form a high-concentration boron added p layer11having a depth L in the outermost front surface, the single-crystal Si substrate10is appressed against a quartz substrate20to be bonded at a room temperature. Chemical etching is performed with respect to the single-crystal Si substrate10from a back surface thereof to set its thickness to L or below. A heat treatment is carried out with respect to an SOI substrate in a hydrogen containing atmosphere to outwardly diffuse B from the high-concentration boron added p layer11, thereby acquiring a boron added p layer12having a desired resistance value. During this heat treatment, B in an Si crystal is diffused to the outside of the crystal in a state where it is coupled with hydrogen in the atmosphere, and a B concentration in the high-concentration boron added p layer11is reduced. In regard to a heat treatment temperature at this time, in view of a softening point of the insulative substrate, an upper limit of the heat treatment temperature is set to 1250° C., and 700° C. is selected as a lower limit of the temperature at which B can be diffused.

REFERENCES:
patent: 5213986 (1993-05-01), Pinker et al.
patent: 5453394 (1995-09-01), Yonehara et al.
patent: 5559043 (1996-09-01), Bruel
patent: 5856229 (1999-01-01), Sakaguchi et al.
patent: 5985728 (1999-11-01), Jennings
patent: 6263941 (2001-07-01), Bryan et al.
patent: 6306729 (2001-10-01), Sakaguchi et al.
patent: 6429095 (2002-08-01), Sakaguchi et al.
patent: 6513564 (2003-02-01), Bryan et al.
patent: 6582999 (2003-06-01), Henley et al.
patent: 2006/0073644 (2006-04-01), Atoji et al.
patent: 0 676 796 (1995-10-01), None
patent: 0 706 203 (1996-01-01), None
patent: B2-3048201 (2000-03-01), None
A.-J. Auberton-Herve et al. “Smart Cut Technology: Industrial Status of SOI Wafer Production and New Material Developments;”Electrochemical Society Proceedings; vol. 99-3 (1999) p. 93-106).
Q.-Y. Tong et al., “Thinning Procedures;”Semiconductor Wafer BondingWiley (1998) pp. 137-172.
Sato et al., “Hydrogen Annealed Silicon-on-insulator”, Applied Physics Letters, vol. 65, No. 15, pp. 1924-1926, (1994).

Affiliated with

Also associated with

Rating

Method for manufacturing SOI substrate does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for manufacturing SOI substrate, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing SOI substrate will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4073786