Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
1999-04-05
2001-05-15
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S435000, C438S700000, C438S704000
Reexamination Certificate
active
06232202
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87118502, filed Nov. 6, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing shallow trench isolation (STI) structure. More particularly, the present invention relates to a method for manufacturing an STI structure with a reduced junction capacitance between source/drain region and substrate.
2. Description of Related Art
A device isolation region is a structure within the substrate that prevents the movement of carriers from one device to its neighbors. For example, device isolation regions are normally formed between metallic oxide semiconductor (MOS) transistors for reducing charge leakage. As the level of integration increases and line width of the device decreases to the sub-quarter micron (0.25 &mgr;m) range, STI is one of the principle means for isolating devices. An STI structure is formed by first performing an anisotropic etching operation to etch out a trench in a semiconductor substrate, and then refilling the trench with insulating material.
FIGS. 1A through 1F
are schematic, cross-sectional views showing the progression of manufacturing steps according to a conventional method of forming a shallow trench isolation structure.
First, as shown in
FIG. 1A
, a pad oxide layer
102
is formed over a silicon substrate
100
. The pad oxide layer
102
will be removed before the gate oxide layer is formed. Thereafter, a silicon nitride (Si
3
N
4
) layer
104
is formed over the pad oxide layer
102
by performing a low-pressure chemical vapor deposition (LPCVD) operation.
Next, as shown in
FIG. 1B
, conventional method is used to form a patterned photoresist layer (not shown in the figure) over the silicon nitride layer
104
. Then, using the patterned photoresist layer as a mask, the silicon nitride layer
104
is etched to form a silicon nitride layer
104
a
. Thereafter, using the silicon nitride layer
104
a
as a hard mask, the pad oxide layer
102
and the silicon substrate
100
are etched sequentially to form a pad oxide layer
102
a
and a trench
106
in the substrate
100
. Hence, active regions
120
for laying the devices are patterned out. Finally, the photoresist layer is removed.
Next, as shown in
FIG. 1C
, a thermal oxidation method is used to form a liner layer
108
on the exposed surface inside the trench
106
. The liner layer
108
extends all the way from the bottom of the trench
106
to the upper corner regions
130
and touches the pad oxide layer
102
a
. In the subsequent step, silicon oxide material is deposited into the trench
106
by performing an atmospheric pressure chemical vapor deposition (APCVD) operation. The silicon oxide layer is then densified by heating to a high temperature, thereby forming an insulation layer
110
.
Next, as shown in
FIG. 1D
, using the silicon nitride layer
104
a
as a polishing stop layer, a chemical-mechanical polishing (CMP) operation is carried out to remove a portion of the insulation layer
110
. Finally, an insulation layer
110
a
is formed inside the trench
106
.
Next, as shown in
FIG. 1E
, hot phosphoric acid (H
3
PO
4
) solution is used to remove the silicon nitride layer
104
a
, and then hydrofluoric acid (HF) solution is used to remove the pad oxide layer
102
a
. Finally, an insulation layer
110
b
, also known as an STI region, is formed inside the substrate
100
.
Next, as shown in
FIG. 1F
, a MOS transistor is formed over the substrate
100
. The MOS transistor includes a gate oxide layer
142
, a gate electrode
140
and source/drain regions
138
. Since the MOS transistor is formed by a conventional method, detailed description of the processing steps are omitted. However, for this type of STI and MOS transistor structure, a large contacting area is normally generated at the junction between the source/drain region
138
(for example, an N-type region) and the substrate
100
(for example, a P-type region). Hence, a large junction capacitance is created there. The larger the junction capacitance, the longer will be the time delay in reaching a stable state. Since a MOS device should not operate until a stable state is reached, operating speed of the device will be lowered.
In light of the foregoing, there is a need to improve the method of forming STI structure.
SUMMARY OF THE INVENTION
Accordingly, the purpose of present invention is to provide a method for manufacturing shallow trench isolation (STI) structure that is capable of reducing junction capacitance between source/drain region and substrate without affecting the overall device layout. Hence, operating speed of the device is increased.
In a second aspect, the purpose of the invention is to provide a method for manufacturing a shallow trench isolation (STI) structure that can increase the degree of electrical insulation between devices in different active regions without affecting the overall device layout.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing shallow trench isolation (STI) structure. The method includes a two-stage etching operation to form the trench. A trench pattern is transferred to a mask layer by etching, and then an anisotropic etching operation is conducted using the patterned mask as an etching mask to form a first trench in the substrate. Spacers are formed on the sidewalls of the first trench. Using the first trench and the sidewall spacers as a hard mask, an isotropic etching operation is carried out to form a second trench underneath the first trench. Hence, a portion of the second trench is able to extend into the substrate below the device area. A liner layer is formed over the exposed substrate surface of the second trench. Insulating material is deposited to fill the first trench and the second trench.
According to one preferred embodiment of this invention, the first trench has a depth of between 500 Å and 3000 Å and the second trench has a depth of between 500 Å and 5000 Å.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5103276 (1992-04-01), Shen et al.
patent: 5112771 (1992-05-01), Ishii et al.
patent: 5629226 (1997-05-01), Ohtsuki
patent: 5910018 (1999-06-01), Jang
patent: 6008131 (1999-12-01), Chen
Huang Jiawei
J. C. Patents
Niebling John F.
Pompey Ron
United Microelectronics Corp.
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