Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1997-11-12
2000-02-15
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438424, H01L 21762
Patent
active
060252499
ABSTRACT:
A method for manufacturing a shallow trench isolation structure comprising the steps of forming a masking layer over a substrate; then, patterning the masking layer to form an opening; thereafter, forming an oxide layer over the surface of the masking layer and the opening; and, etching back the oxide layer to form oxide spacers on the sidewalls of the masking layer. Subsequently, the substrate is etched downward along the side edges of the oxide spacers to form a trench. Thereafter, the oxide spacers are removed to expose the substrate surface formerly blocked by the oxide spacers. Finally, a liner oxide layer is formed on the trench surface over the substrate. The characteristic of this invention is the formation of a smoother and thicker liner oxide layer. Hence, device current leakage due to subthreshold current and associated kink effect can be avoided.
REFERENCES:
patent: 5521422 (1996-05-01), Mandelman et al.
patent: 5677233 (1997-10-01), Abiko
patent: 5801083 (1998-09-01), Yu et al.
patent: 5834358 (1998-11-01), Pan et al.
Fourson George
United Microelectronics Corp.
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