Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-12-14
2001-09-11
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S719000
Reexamination Certificate
active
06287938
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor memory device; and, more particularly, to a method for manufacturing a shallow trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
DESCRIPTION OF THE PRIOR ART
As is well known, a dynamic random access memory (DRAM) having a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization.
Therefore, as the device dimension becomes reduced in the memory cell, the dimensions of active regions and the space therebetween are accordingly reduced as well. Isolation regions, which play an important role in preventing current leakage between two adjacent devices, become narrow which results in several problems occurring mainly due to the high integration of the device. The narrow isolation structure is thinner for a field oxide (FOX) layer in the narrow space between the adjacent active regions. Therefore, the FOX layer cannot effectively perform its isolation. Moreover, during the formation of the FOX layer, a bird's peak occurs at the edge of the active region so that a current leakage may occur on the gate oxide layer.
To overcome the above problem, a trench isolation structure is proposed and widely used for the semiconductor memory device with high integration, e.g., 1 Gigabit DRAM to 4 Gigabit DRAM application, wherein a trench region is formed in a silicon substrate of the semiconductor with a depth that is enough for isolating the adjacent devices.
Therefore, a method for manufacturing the conventional trench isolation comprises the steps of forming a pad oxide or nitride layer on a silicon substrate, selectively etching the pad oxide or nitride layer, and dry etching the silicon substrate by using the patterned pad oxide or the nitride layer as a mask.
The conventional trench isolation has a drawback, which is that a compressive stress concentrates on a bottom portion of the trench due to thermal budget during processes, such as annealing and other thermal treatment processes. Therefore, defects in the silicon substrate move easily so that the morphology of the trench sidewall deteriorates and dislocations occur easily. Dislocations are apt to occur more easily due to the concentration of the compressive stress around the bottom portion of the trench when the trench experiences the thermal budget.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a method for manufacturing a trench isolation in a semiconductor device with an enhanced profile, whereby residual stress concentration is capable of being prevented.
In accordance with one aspect of the present invention, there is provided a method for manufacturing a trench isolation, the method comprising the steps of: a) forming a wide rounded convex shape at an upper portion of the trench by a first etching of high polymerization; b) forming a vertical sidewall at the middle of the trench by a second etching of low polymerization; and c) forming a narrow rounded concave shape at the bottom portion of the trench by a third etching of high polymerization.
REFERENCES:
patent: 5618379 (1997-04-01), Armacost et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5807789 (1998-09-01), Chen et al.
Kang Byoung-Ju
Lee Ki-Yeup
Hyundai Electronics Industries Co,. Ltd.
Jacobson & Holman PLLC
Niebling John F.
Roman Angel
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