Method for manufacturing semiconductor package substrate

Details Method for manufacturing semiconductor package substrate Method for manufacturing semiconductor package substrate

2008-07-15

2008-07-15

Graybill, David E (Department: 2822)

Electrolysis: processes, compositions used therein, and methods

Electrolytic coating

Coating selected area

C029S846000, C029S847000, C427S096100, C427S097100, C427S097300, C427S097400, C427S097500

Reexamination Certificate

active

07399399

ABSTRACT:
A method for manufacturing a semiconductor package is proposed. A circuit board with a circuit layer on at least one surface thereof is provided. The circuit board has at least one free area, and the circuit layer has a plurality of electrically connecting pads distributed on the periphery of the free area. A metal protecting layer is plated on the electrically connecting pads by non-plating line. The free area is removed, to form a cavity penetrating the circuit board. The present invention prevents burrs which may otherwise form on the periphery of a cavity, to increase the yield and throughput.

REFERENCES:
patent: 6214525 (2001-04-01), Boyko et al.
patent: 7216424 (2007-05-01), Wang
patent: 2004/0080031 (2004-04-01), Huang et al.
patent: 2004/0134682 (2004-07-01), En et al.
patent: 2005/0253284 (2005-11-01), Wang et al.
patent: 2006/0006422 (2006-01-01), Chu et al.
patent: 2006/0134888 (2006-06-01), Wu et al.

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