Method for manufacturing semiconductor memory device having a st

Details Method for manufacturing semiconductor memory device having a st Method for manufacturing semiconductor memory device having a st

1992-10-13

1993-06-15

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 48, 437 60, 437919, H01L 2170

Patent

active

052197816

ABSTRACT:
A capacitor of a semiconductor memory device includes a planar type capacitor portion formed on a surface of an impurity region and a stacked type capacitor portion extending above the gate electrode. The stacked capacitor portion has a three-layer structure of polycrystalline silicon in which upper, lower and side surfaces of a lower electrode are surrounded by a dielectric layer and the upper electrode. A portion of a dielectric layer in the stacked capacitor portion is coupled to another dielectric layer formed on the surface of one impurity region. The capacitor has a planar type capacitor provided in the planar area of occupation of the stacked capacitor portion, whereby the capacitance of the capacitor can be increased without increasing the planar area of occupation.

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IEDM Publication entitled "3-Dimensional Stacked Capacitor Cell for 16M and 64M DRAMS," by T. Ema et al., 1988, pp. 592-595.
T. Kisu, "A Novel Storage Capacitance Enlargement Structure Using a Double-Stacked Storage Node In STC Dram Cell", 20th Int'l. Conference on Solid State Devices and Materials, 1988, pp. 581-584.

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