Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2011-04-19
2011-04-19
Lee, Cheung (Department: 2812)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S128000, C438S288000, C438S435000, C257SE21540, C257SE21585, C257SE21679
Reexamination Certificate
active
07927967
ABSTRACT:
A method for manufacturing a semiconductor memory device, includes: forming a stacked unit above a semiconductor substrate; making a hole in the stacked unit to pass through electrode layers and insulating layers of the stacked unit; forming an insulating film on a side wall of the hole, the insulating film including a charge storage layer; forming a semiconductor layer in an interior of the hole to align in a stacking direction of the electrode layers and the insulating layers to form a memory string; making a trench in a portion of the stacked unit proximal to the memory string to pass through the electrode layers and the insulating layers; forming a metal film on a side wall of the trench; forming a cap film to cover the metal film and fill into the trench; performing heat treatment to form a compound on the side wall of the trench.
REFERENCES:
patent: 2007/0158736 (2007-07-01), Arai et al.
patent: 2010/0207185 (2010-08-01), Lee et al.
patent: 2008-171918 (2008-07-01), None
Kim, J. et al., Novel 3-D Structure for Ultra High Density Flash Memory with VRAT (Vertical-Recess-Array-Transistor) and PIPE (Planarized Integration on the samePlanE), 2008 Symposium on VLSI Technology Digest of Technical Papers, pp. 122-123, (2008).
Matsuyama Hideto
Nomura Kayo
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lee Cheung
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