Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-04-25
2002-06-04
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S253000, C438S240000
Reexamination Certificate
active
06399399
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor memory devices and more particularly to a method for manufacturing a capacitor in a semiconductor memory device.
BACKGROUND OF THE INVENTION
Semiconductor devices including both memory and logic products are developed with what is known as large scale integration (LSI) in which millions of devices can be integrated on a single chip. In these cases, much effort has been put forth in developing manufacturing technology in order to build these semiconductor devices. In particular, efforts have been made at developing technology that will enable denser semiconductor memory devices to be manufactured.
Semiconductor memories having a random access can be divided into DRAM (dynamic random access memory) and SRAM (static random access memory). These semiconductor memories are typically developed using MOS (metal oxide semiconductor) transistors, due to their superior integration capabilities and/or lower power consumption. A DRAM typically has a smaller cell size than an SRAM, which allows a DRAM to have a denser memory size and can typically store more bits on a single chip. This allows a lower cost per bit and makes DRAM the preferred semiconductor memory in many applications.
In a DRAM, a memory cell (DRAM cell) has a memory cell transistor (pass transistor) and a capacitor (storage capacitor). The capacitor is connected to the memory cell transistor and is used for storing information. The data value of information stored in a DRAM cell is determined by the presence or absence of charge on the capacitor. Capacitors having a MIM (metal-insulator-metal) structure are widely adopted.
The cost per unit of DRAM can be lowered by increasing the number of DRAM chips that can be manufactured on a single wafer and/or by increasing the amount of data that can be stored on a single DRAM chip. In order to increase the volume of information that can be stored on a single DRAM and/or decrease the cost per bit in a DRAM by decreasing chip size, smaller memory cells are desired. However, as memory cell size decreases, the area of the cell capacitor also decreases. The decrease in capacitor size typically decreases the capacitance. Thus, the capacitor can store less charge. This affects the integrity of the data stored in a DRAM cell. External noise and/or other affects can introduce errors (known as soft errors) in the stored information due to the critical charge required to properly determine a logic value in a DRAM cell.
In order to increase the capacitance of the cell capacitor in a DRAM, high dielectric insulation films have been used as the dielectric for cell capacitors. High dielectric insulation films are typically various forms of oxide films such metal oxides such as tantalum oxide (Ta
2
O
5
), lead zirconium titanate (PZT), barium titanate (BTO), and strontium titanate (STO). For example, silicon oxide/dioxide (SiO
2
) has been used as the dielectric for cell capacitors for many years. Tantalum oxide has a dielectric constant that is approximately ten times higher than the dielectric constant of silicon dioxide. Furthermore, the dielectric constant of tantalum oxide is about four times higher than that of silicon nitride, which has been used to increase the capacitance of the DRAM cell capacitors.
The capacitance of the cell capacitors can also be increased by increasing the area of the upper and/or lower capacitor electrodes. This can be done by utilizing three-dimensional structures such as cylindrical, boxy, or fin type shapes. The capacitance can be increased even further by combining such a three-dimensional structure with a high dielectric constant insulation film.
A conventional method of making a semiconductor memory (DRAM) cell will now be explained with reference to
FIGS. 12A
to
14
F.
FIGS. 12A
to
14
F illustrate cross-sections of a conventional DRAM cell after various process steps have been completed.
Referring now to
FIG. 12A
, a P-type silicon substrate
51
has pass transistors
60
formed in a memory array region. A separation insulation film
52
such as silicon oxide formed on the substrate base
51
by LOCOS (local oxidation of silicon) method. Inside each active region surrounded by the separation insulation film
52
, a gate oxide film
53
and a gate electrode (word line)
54
are formed. A plurality of N-type diffusion regions
55
forming a source region or drain region for transistors
60
are selectively formed. The surface of the device is then covered by an interlayer insulation film
56
.
In this manner, an array of MOS-type memory cell transistors
60
are formed. Each include a gate (control) electrode
54
and a plurality of N-type diffusion regions
55
forming source/drain regions.
A contact hole
57
is then formed in the interlayer insulation film
56
, so as to allow a later formed capacitor to make an electrical contact with N-type diffusion region
55
. A capacitor contact
58
, comprising polycrystalline silicon, is then formed in the contact hole
57
. A silicon oxide nitride film
61
and plasma oxide film
62
is then formed on the interlayer insulation film
56
and a cylindrical groove
63
is formed through the plasma nitride-oxide film
61
and the plasma silicon oxide film
62
so as to expose the capacitor contact
58
.
Referring now to
FIG. 12B
, a barrier film
65
comprised of a laminated film of TiN/Ti (titanium nitride/titanium) is then formed over the entire surface by means of CVD (chemical vapor deposition). Then, by sputtering only or sputtering in combination with CVD, a lower electrode film
66
A is formed over the entire surface. Lower electrode film
66
A is fabricated into a lower electrode of a predetermined pattern by patterning in a later process.
Referring now to
FIG. 13C
, a deposition process is performed so as to embed a resist material
67
inside each cylindrical groove
63
.
Referring now to
FIG. 13D
, the surface of interlayer insulation film
62
is then planarized by etching to remove unneeded regions of barrier film
65
and lower electrode
66
.
Referring now to
FIG. 14E
, resist material
67
inside cylindrical groove
63
is removed by ashing using an oxygen (O
2
) plasma.
Referring now to
FIG. 14F
, a capacitance insulation film
68
and an upper electrode film
69
A comprising Ta
2
O
5
are then formed over the entire surface with CVD. Then, an upper electrode (not shown) is formed by patterning the upper electrode film
69
A into a desired pattern. This completes the manufacturing of memory cell capacitors of a semiconductor memory.
However, the semiconductor memory produced by the afore-mentioned conventional process can have a drawback of inferior leakage current in the capacitor. This can be caused by the ashing of resist film
67
during the step of applying an oxygen plasma (
FIG. 14E
) after the planarizing step (FIG.
13
D). This can cause the surface of lower electrode
66
to be degraded by damage introduced by the oxidizing plasma. Because capacitor insulation film
68
is formed on the degraded surface of lower electrode
66
, the quality of capacitor insulation film
68
can also be degraded by the influence of the damaged lower electrode
66
. These effects can cause the capacitor leakage current to increase. Such an increase in capacitor leakage current can cause charge to leak from the storage capacitor and can reduce read margins. This can destroy the integrity of data stored on the semiconductor memory, in particularly under “pause” conditions.
A method of manufacturing a semiconductor memory device to prevent such effects of degradation of the lower electrode produced during ashing has been disclosed in a Japanese Unexamined Patent Application, First Publication, No. Hei 7-94600 (JP 7-94600). This process will now be explained with reference to
FIGS. 15A
to
18
H.
FIGS. 15A
to
18
H illustrate cross-sections of a conventional DRAM cell after various process steps have been completed.
Referring now to
FIG. 15A
, a silicon substrate
131
has memory cell transistors
130
formed in a memory array r
NEC Corporation
Tsai Jey
Walker Darryl G.
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