Method for manufacturing semiconductor integrated circuits inclu

Details Method for manufacturing semiconductor integrated circuits inclu Method for manufacturing semiconductor integrated circuits inclu

1987-03-23

1990-01-09

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 34, 437 59, 437 56, 437 57, 437 74, 437 75, 437 77, 437153, 437149, 437154, H01L 2170, H01L 2176

Patent

active

048928364

ABSTRACT:
This method, requiring a reduced number of process phases and providing an efficient, high-voltage structure, comprises forming a P-well region of the N-channel transistor of a CMOS device, by means of boron atom implant through a protective mask, forming at least one insulation region surrounding the CMOS device, forming edge regions having the same conductivity type as the insulation region but with a smaller concentration of impurities on at least one part of the insulation region and in the high-voltage electronic devices by means of the same boron atom implant used to form the P-well region.

REFERENCES:
patent: Re30282 (1980-05-01), Hunt et al.
patent: 4021270 (1977-05-01), Hunt et al.
patent: 4054899 (1977-10-01), Stehlin et al.
patent: 4325180 (1982-04-01), Curran
patent: 4346512 (1982-08-01), Liang et al.
patent: 4628341 (1986-12-01), Thomas
patent: 4694562 (1987-09-01), Iwasaki et al.

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