Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Complementary bipolar transistors
Reexamination Certificate
2001-09-05
2003-03-04
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Complementary bipolar transistors
C438S341000, C438S360000, C438S413000, C438S424000, C438S430000, C438S455000
Reexamination Certificate
active
06528379
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same realizing high with stand voltage in an dielectric-isolated complementary bipolar transistor by provision of thickened collector region.
In recent years, a high with stand voltage and a high-degree of integration of transistors used in an audio amplifier, a display driver, etc. have been demanded. High degree of integration and high speed of a high withstand voltage (or high voltage) integrated circuit is preferably realized by the dielectric isolation technique in order to prevent a parasitic transistor from being formed and prevents a chip size from being increased owing to element isolation.
FIG. 13
shows a sectional view of a conventional typical semiconductor integrated circuit device (e.g. Japanese Patent Publication No. 11-354535). Now referring to
FIGS. 14-20
, an explanation will be given of a method for manufacturing the semiconductor integrated circuit device shown in FIG.
13
.
FIG. 14
shows an area where a high voltage vertical NPN vertical transistor is to be formed and another area where a high voltage vertical PNP transistor is to be formed. First, a buried oxide film
2
having a thickness of about 2 &mgr;m is formed on the surface of an N type substrate
3
of Si by thermal oxidation. The N type substrate is bonded to a supporting substrate
1
through the buried oxide film
2
at room temperature. The N type substrate
3
will be changed into an N
+
type buried layer
4
and a P
+
type buried layer
5
, which are active layers, by the subsequent step. The N type substrate
3
may be a silicon substrate having e.g. resistivity of about 10 &OHgr;·cm. Thereafter, the substrate
3
is annealed in an atmosphere of oxygen e.g. for about two hours at 1000° C. to increase the bonding strength between the buried oxide film
2
and supporting substrate
1
. Further, the thickness of the N type substrate
3
is reduced to a prescribed thickness, e.g. 2 &mgr;m by e.g. mechanical polishing or chemical-mechanical polishing (CMP).
Next, ion implantation is executed in order to form an N
+
buried layer
4
. Specifically, by known photolithography, using as a mask photoresist (not shown) with an opening at an NPN transistor section, N type impurities of e.g. arsenic (As) are ion-implanted at an accelerating voltage of 50 keV and dose of 3×10
15
/cm
2
. Thereafter, the photoresist is removed. Further ion-implantation is executed to form a P
+
type buried layer
5
. Specifically, by known photolithography, using as a mask photo resist (not shown) with an opening at a PNP transistor section, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 50 keV and dose of 3×10
15
/cm
2
. Thereafter, the photoresist is removed.
Subsequently, the substrate is annealed in an atmosphere of water vapor e.g. for about one hour at 1100° C. so that the arsenic introduced in the NPN transistor section and boron introduced in the PNP transistor section in the previous step are thermally diffused, respectively, thereby forming the N
+
type buried layer
4
and the P
+
type buried layer
5
. In this annealing step, an oxide layer (not shown) is formed on the surface of the active layer. So, this oxide layer is removed by light etching using e.g. a hydrofluoric acid solution, which results in a structure as shown in FIG.
14
.
Next, as shown in
FIG. 15
, an N type epitaxial layer
6
having resistively of 10 &OHgr;·cm and a film thickness of 15 &mgr;m is grown on the N
+
type buried layer
4
and the P
+
type buried layer
5
which are the active layers. The NPN transistor section of the N type epitaxial layer
6
constitutes an N type collector region
7
, whereas the PNP transistor section of the N type epitaxial layer
6
is changed into a P type collector region
8
by the subsequent step. Specifically, an oxide film
9
having a thickness of 50 nm is formed by thermal oxidation. By known photolithography, using as a mask photoresist with an opening at a PNP transistor section, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 300 keV and dose of 8×10
12
/cm
2
. The substrate is annealed in an atmosphere of inert gas for e.g. 7 (seven) hours at 1200° C. to form the P type collector region
8
of the PNP transistor, which results in a structure as shown in FIG.
15
.
By known photolithography, using as a mask photoresist with an opening on a base portion of the NPN transistor, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 40 keV and dose of 1×10
14
/cm
2
. After the photoresist has been removed, by known photolithography, using as a mask photoresist with an opening on a base region of the PNP transistor, N type impurities of e.g. phosphorous (P) are ion-implanted at an accelerating voltage of 60 keV and dose of 1×10
14
/cm
2
. After the photoresist has been removed, the substrate is annealed in an atmosphere of inert gas for e.g. 30 minutes at 900° C. As a result, the impurities are thermally diffused to form a P type base region
10
of the NPN transistor and an N type base region
11
of the NPN transistor, respectively.
Next, by known photolithography, using as a mask photoresist with openings on an N type emitter region and an N type collector contact of the NPN transistor, N type impurities of e.g. arsenic (As) are ion-implanted at an accelerating voltage of 110 keV and dose of 5×10
15
/cm
2
. Thereafter, the photoresist is removed. Subsequently, by known photolithography, using as a mask photoresist with openings on a P type emitter region and a P type collector contact of the PNP transistor, P type impurities of e.g. boron (B) are ion-implanted at an accelerating voltage of 40 keV and dose of 3×10
15
/cm
2
. After the photoresist has been removed, the substrate is annealed in an atmosphere of inert gas for e.g. about 30 minutes at 1000° C. As a result, the impurities are thermally diffused to form an N
+
type emitter region
12
and an N
+
type collector contact
13
of the NPN transistor, and a P
+
type emitter region
14
and P
+
type collector contact of the PNP transistor, respectively. Thus, the structure as shown in
FIG. 16
results.
Thereafter, the oxide layer
9
, N type collector layer and N
+
type buried layer
4
of the NPN transistor section are etched to reach the buried oxide layer
2
, thereby forming a trench
16
for element isolation. Simultaneously, the oxide layer
9
, P type collector layer
8
and P type buried layer
5
of the PNP transistor section are etched to reach the buried oxide layer
2
, thereby forming a trench
16
for element isolation. The trenches
16
are formed so that the sides of the collector contacts
13
and
15
are exposed within the trenches
16
, respectively. Thus, the structure as shown in
FIG. 17
results.
Next, by e.g. thermal oxidation, an oxide film
17
having a thickness of about 500 nm is formed on the inner wall of the trench
16
. Further, the oxide film
17
abutting on the collector contacts
13
and
15
of the NPN transistor and PNP transistor is removed by etching. Thus, the structure as shown in
FIG. 18
results. By e.g. Chemical Vapor Deposition (CVD), poly-Si
18
is deposited to be buried within the trench
16
with the oxide film
17
. Thereafter, the poly-Si
18
which has overflowed is etched back by Reactive Ion Etching (RIE) to flatten the substrate surface. Thus, the structure as shown in
FIG. 19
results.
N type impurities are introduced into the poly-Si
18
buried in the trench
16
which abuts on the N
+
type collector contact
13
of the NPN transistor. Specifically, by known photolithography, using as a mask photoresist with an opening at the trench, N type impurities of e.g. phosphorous (P) are ion-implanted at an accelerating voltage 180 keV and dose of 5×10
15
/cm
2
. Further, P type impurities are introduced into the poly-Si
18
Fujinuma Chikao
Hata Hirotsugu
Kitamura Osamu
Okawa Shigeaki
Takada Tadayoshi
Doan Theresa T.
Fish & Richardson P.C.
Sanyo Electric Co,. Ltd.
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