Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
1999-11-12
2001-11-06
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S565000
Reexamination Certificate
active
06313004
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices and more particularly to such a method for manufacturing semiconductor devices that includes a step of doping impurities at a high concentration to hemi-spherical grained silicon (hereinafter abbreviated as HSG-Si: Hemi-Spherical Grained Si).
2. Description of the Related Art
There has been a demand recently for even higher integration densities of dynamic random access memories (DRAM's) and other semiconductor devices by increasing the electrostatic capacitance of a unit area of the component capacitor of each memory cell. To meet the demand, such a method has been adopted that increases the electrostatic capacitance by forming in a cylindrical shape either one of the upper and lower electrodes making up each capacitor, for example the lower electrode. According to another method, on the capacitor's surface of the electrode often made of polycrystal silicon are formed HSG-Si to provide irregularities in that surface in order to increase the surface area of the electrode, thus trying to increase the electrostatic capacitance. In this case, however, when HSG-Si is depleted, its electric resistance is increased, thereby preventing the capacitor's capacitance from being sufficiently increased. Usually, therefore, a diffusion method or an ion implantation method is used to dope impurities such as phosphorus into HSG-Si to reduce its electrical resistance.
A technology by means of a diffusion method for doping impurities into HSG-Si grains is disclosed in Japanese Laid-Open Patent Application No. Hei 9-289292. A method, described in this publication, for manufacturing semiconductor devices sequentially comprises steps of: forming inter-layer insulator films on a semiconductor substrate; forming cell contacts; forming polycrystal silicon films having irregularities in the surface; forming an oxidized film of silicon (hereinafter called PSG: Phospho Silicated Glass) on the above-mentioned polycrystal silicon film; diffusing impurities from this PSG film into the irregularly-surfaced polycrystal silicon film; and removing the PSG films. According to this manufacturing method, PSG films must undergo heat treatment at a temperature of about 800-950° C. for about 10-60 minutes.
SUMMARY OF THE INVENTION
Unlike the case of standalone DRAM devices, where there are not so severe restrictions on the temperature of heat treatment during the manufacturing processes, in the case of logic-mixed memory devices in which DRAM's and logic LSI's are mounted on the same chip, there are needs to set the heat treatment temperature at a low value or the heat treatment time at a short value in order to protect the transistors of a logic portion which have a short gate length liable to suffer from fluctuations in the threshold voltage and the characteristics. As shown in
FIG. 8
, for example, when heat treatment is conducted on transistors with a gate length of 0.25 &mgr;m, the transistors' threshold voltage (Vth) has roughly a constant value up to a heat treatment temperature of about 780° C., whereas in excess of 780° C. the threshold voltage would drop rapidly. The conventional manufacturing methods described in the above-mentioned publication, however, carry out the heat treatment at a high temperature of about 800-950° C. for several tens of minutes in the doping of phosphorus, to cause changes in the threshold voltage of the logic-portion transistors, thus disqualifying themselves for use in the manufacturing of the above-mentioned logic-mixed memory devices.
With the method described in the above-mentioned publication, on the other hand, whereby phosphorus is diffused under the usually employed conventional conditions without forming PSG films on the HSG-Si surface, PSG-Si films are for sure formed on the HSG-Si surface but, at the same time, a lot of silicon atoms are dissipated from the HSG-Si side when the PSG films are grown, so that as the PSG films grow, a larger amount of the HSG-Si is lost, finally resulting in a small amount of the HSG-Si being left when the surface PSG films are removed. By this reason, even if HSG-Si grains are formed, the irregularities in the electrode surface are reduced small, thus causing a problem that the capacitance cannot sufficiently be increased even with increases in the area of the electrode surface.
FIG. 9
summarizes the (C-V) characteristics of capacitors formed by the above-mentioned conventional methods.
In the figure, a curve (A) indicates the characteristics of a capacitor having flat surfaces with no HSG-Si formed on its electrode surfaces. This curve shows a lower value of overall capacitance. A curve (B), on the other hand, indicates the characteristics of another capacitor on which is formed HSG-Si containing no impurities on the electrode surfaces. As indicated by this curve, thus formed HSG-Si increased overall capacitance as compared to the case of (A) but no impurities introduced in the HSG-Si caused depletion in the HSG-Si grains, thus resulting in large decreases in the capacitance when a negative voltage is applied to the electrode.
As against this, a curve (C) indicates the characteristics of still another capacitor with phosphorus introduced in HSG-Si. One example of diffusion phosphorus is: temperature: 750° C., an atmosphere of a gas of N
2
, POCl
3
, and O
2
in a mixture, flow rate being 20 slm for N
2
, 300 mg/m for POCl
3
, 400 sccm for O
2
, diffusion time being 30 minutes. In this case, the mole ratio of O
2
/POCl
3
was about 8. In the case of the curve (C), some phosphorus introduced in HSG-Si suppressed the depletion on the negative voltage side to bring about flattened characteristics, with a low absolute value of the capacitance on the positive voltage side as compared to the curve (B) though. The possible reason is that although phosphorus introduced suppressed depletion, the surface area of the capacitor was decreased by such a plurality of synergetic effects that the HSG-Si grains are reduced due to the etching of silicon caused by Cl radicals generated from POCl
3
in a gas being processed at the time of the diffusion of phosphorus, and that a larger partial pressure of O
2
and the accelerated oxidation of halogens increased the oxidation amount (loss amount) of the grains, and other factors. The rate of capacitance decreases was 15%-40% approximately.
Thus, it was difficult by the conventional methods to establish at the same time such two conditions of doping impurities into HSG-Si to suppress the depletion of HSG-Si and of inhibiting the reduction of the HSG-Si.
In view of the above-mentioned problems, an object of the present invention is to provide a method for manufacturing semiconductor devices that even with heat treatment of a relatively low temperature, it is possible to dope impurities to HSG-Si and also to subsequently inhibit the reduction of the HSG-Si grains.
To achieve the above-mentioned object, the present inventor has already applies such a “method for manufacturing semiconductor devices” that HSG-Si is formed on the surface of the lower electrode of a capacitor and then a thin CVD-oxidized film is formed on the HSG-Si surface, through which CVD-oxidized film is diffused phosphorus into the HSG-Si in a solid phase. According to this method, since phosphorus is constantly supplied into the CVD-oxidized film from an atmospheric gas containing phosphorus, the phosphorus concentration is not decreased with elapse of time, thus making it possible to dope phosphorus into the HSGO-Si in a stable manner. At the same time, the CVD-oxidized film functions as a buffer layer against the oxidation involved in the diffusion of phosphorus to suppress the dissipation of the silicon atoms from the HSG-Si grains, thus preventing the reduction of the HSG-Si.
Although this method achieves the above-mentioned object, it requires a step of forming on the HSG-Si surface a CVD-oxidized from which acts as a buffer layer, which may be called a film to prevent the l
Chaudhuri Olik
NEC Corporation
Trinh (Vikki) Hoa B.
Young & Thompson
LandOfFree
Method for manufacturing semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor devices will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2584141