Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Assembly of plural semiconductive substrates each possessing...
Reexamination Certificate
1999-08-02
2001-05-15
Picardat, Kevin M. (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Assembly of plural semiconductive substrates each possessing...
C438S612000, C438S613000
Reexamination Certificate
active
06232147
ABSTRACT:
TECHNICAL FIELD
This invention relates to a reliable semiconductor device and a method of manufacturing such semiconductor device. In one mode, the invention relates to a semiconductor device and in particular to a semiconductor device having a structure that permits rearrangement of pads for connecting semiconductor chips, and a method for manufacturing such semiconductor device. In the other mode, the invention relates to a semiconductor device whose semiconductor chip or chips may be mounted on a printed circuit board by means of an area array bump structure which has a multiplicity of solder bumps in the form of grid.
BACKGROUND OF THE INVENTION
The first mode of the invention will be now described.
In manufacturing electronic devices, wire bonding technology has been utilized in packaging an LSI chip or chips on a semiconductor substrate. The electronic devices are provided with pads for electrical connection of the devices with external lead wires which are made of a material containing aluminum as a major composition. So-called tape Automated Bonding (TAB) technology and Flip Chip technology are also used in packaging LSIs. All of these techniques commonly utilize bumped electrodes which are formed on the pads.
It is noted that these pads must be positioned in an adequate arrangement suitable not only for a design of the LSI but also for a particular bonding technique used, since the arrangement of such pads generally depends on the type of the packaging technology used.
This implies that even those LSI chips having an identical basic structure and identical functions must be packaged in different ways if they are packaged by different techniques. They would then require different packaging designs and additional product management as if they were different LSIs. This would in turn add undesirable complexity and increased cost to the management of the products, thereby rendering the final LSIs costly.
Accordingly, it would be advantageous to provide chips that may be equally packaged by different types of packaging techniques, thereby unaffected by the disadvantages mentioned above.
One way to achieve this feature is disclosed in Japanese Patent Publication Laid Open Nos. 2-121333 and 5-218042, in which the chip is provided with primary pads at positions independent of packaging techniques, and the pads are rearranged in accordance with the packaging technique employed.
Briefly, the pad rearrangement techniques as disclosed in the foregoing patents are based on the formula in which lead wires are formed on a protective insulation substrate having openings or through-holes for primary pads, and additional or secondary pads are mounted on the lead wires extending between the primary pads and secondary pad sites away from the primary pads, so that external lead wires may be connected to the secondary pads at arbitrary positions.
Briefly, these pad rearrangement techniques are based on the formula that additional pads or secondary pads are mounted on lead wires at arbitrary positions away from the original pads so that external lead wires may be connected at those arbitrary positions. These secondary pads are formed on a protective insulation substrate laid on the substrate and having openings for the primary pads.
In the prior art techniques mentioned above, the lead wires have a multi-layered lead structure, which consists of, for example, three layers of titanium (Ti), nickel (Ni), and gold (Au), or two layers of titanium and copper (Cu), deposited in the order mentioned.
Similar prior art techniques for multi-layered lead wires have been also disclosed in Japanese Patent Publication Laid Open Nos. 60-136339, 57-122542, 62-183134, and 1-290232.
The first of these publication concerns with Ti—Cu—Ni layers; the second with Ti—Cu—Ti layers; the third with Ti—Pd—Ti layers; and the last with Al—V—Al layers and Al—Ti—Al layers.
It should be kept in mind, however, that the secondary pads must be necessarily located at sites above the corresponding active semiconductor circuit element (or active component), and hence that the active component must be protected from the weight of the pads plus the bonding load acting on the active component during bonding of the external lead wires onto the secondary pads.
It should be also kept in mind that the sheet resistance of the lead wires must be sufficiently low, since otherwise the lead wires acquire high resistance due to the fact that the secondary pads must be properly spaced apart from their primary pads, so that the lead wires extending between them can be long.
Further, it should be noted that the secondary pads must have good adhesive power to bumps to be formed on the pads.
Still further, the rearrangement structure of the lead wires for the secondary pads must have a structure that may prevent electromigration between them, especially in the case where the chip density of the LSI is increased and accordingly the spacing between the lead wires is decreased. Particularly, the lead wires containing Cu, Au or Ag must have a structure immune to such electromigration.
However, any of the prior art lead wire structures can not satisfy these requirements altogether. There is accordingly a need for a semiconductor device having a novel lead wire structure which meets all the requirements.
The second mode of the invention will be now described.
There have been known many types of techniques for mounting semiconductor chips or electronic devices such as LSIs on a printed circuit board. Choice of an appropriate technique depends on the particular terminal arrangement of the electronic devices to be mounted.
A well known terminal arrangement for electronic devices like LSIs is a peripheral type terminal arrangement, in which terminals extend outwardly from the periphery of the package. A typical example of this type is a quad flat package (QFP).
However, in order to meet a recent requirement for miniaturization of electronic devices and for high density packaging thereof, a mounting technique utilizing so called “face down” solder bumps has been frequently used because these bumps permit of external connection of the terminals and occupy a relatively small mounting area. The solder bumps are mounted on bump lands or terminals provided on an insulation layer. Thus, each of the bump lands needs a predetermined area. Now that an electronic device such as LSI has a very large number of gates, it necessarily has many input and output terminals. Therefore, the electronic device is mounted using a bump grid array in which the bump lands are arranged in the form of generally planar grid in order to arrange many bump lands neatly on the insulation layer. This type of bump structure is also called area array bump structure.
An example of such area array bump structure is shown in
FIG. 6A
, which shows in a partial side elevational cross section a major portion of a semiconductor device having a conventional solder bump structure. Formed together with various bonding pads and lines on an insulation substrate
52
of a material such as polyimide, is a plurality of bump lands
53
for mounting thereon solder bumps.
A semiconductor chip such as LSI (not shown) is die-bonded at a predetermined position on the top surface of the insulating material
52
, using appropriate glue.
The terminals of the semiconductor chip and the bonding pads (not shown) formed on the insulation substrate
52
are electrically connected as needed by means of, for example, an appropriate wire bonding technology. In order to increase the reliability of the electronic device, it is coated with a sealing resin
51
.
Each of the bump land
53
is provided with a small through-hole or opening
55
formed in the insulation substrate
52
, which is smaller in area compared to the bump land
53
. Solder bumps
54
are bonded on the bump lands
53
in the respective openings
55
by overturning the insulation substrate
52
, placing the solder bumps
54
in the respective through-holes
55
, and applying solder re-flow treatment.
The diameter of each through-hole is constant throughout
Imamura Kazuyuki
Kado Kenichi
Matsuki Hirohisa
Watanabe Eiji
Yurino Takahiro
Armstrong Westerman Hattori McLeland & Naughton LLP
Collins D. M.
Fujitsu Limited
Picardat Kevin M.
LandOfFree
Method for manufacturing semiconductor device with pad... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device with pad..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device with pad... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2565868