Method for manufacturing semiconductor device with overlay...

Details Method for manufacturing semiconductor device with overlay... Method for manufacturing semiconductor device with overlay...

2006-12-21

2009-02-03

Smith, Bradley K (Department: 2894)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S462000, C257SE21546

Reexamination Certificate

active

07485543

ABSTRACT:
A method for manufacturing a semiconductor device comprising dishing a part of a center of an isolation oxide film to form an overlay vernier having a step difference, prevents an attack in a CMP process of a gate polysilicon layer and improves an overlay characteristic due to the right-and-left symmetrical structure of the overlay vernier.

REFERENCES:
patent: 2006/0057815 (2006-03-01), Kim
patent: 2006/0148275 (2006-07-01), Han et al.
patent: 60229334 (1985-11-01), None
patent: 100170734 (1998-10-01), None
patent: 1020020043779 (2002-06-01), None
patent: 1020040057634 (2004-07-01), None

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