Method for manufacturing semiconductor device utilizing selectiv

Metal working – Method of mechanical manufacture – Assembling or joining

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29578, 29580, 29591, 148174, 148175, 148187, 148188, 156628, 156647, 156649, 156657, 357 35, 357 50, 357 59, 357 92, H01L 21225, H01L 21302

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044334702

ABSTRACT:
A method of manufacturing a semiconductor device wherein grooves are formed between vertical type-npn transistors and insulating oxide layers are formed on the bottoms of the grooves, thereby preventing parasitic p-n junctions, which is characterized in that said grooves are formed by using as a mask a conductive pattern containing an impurity for forming an impurity region or by using as a mask an insulating film formed by the annealing of the conductive pattern.

REFERENCES:
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patent: 4284997 (1981-08-01), Nishizawa
patent: 4318751 (1982-03-01), Horng
patent: 4333227 (1982-06-01), Horng et al.
patent: 4338138 (1982-07-01), Cavaliere et al.
patent: 4338618 (1982-07-01), Nishizawa
patent: 4378630 (1983-04-01), Horng et al.
patent: 4398338 (1983-08-01), Tickle et al.
Berger et al., "Investigation of Intrinsic Delay . . . MTL/I.sup.2 L", IEEE J. Solid-State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 327-336.

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