Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1996-03-04
1998-08-18
Bowers, Jr., Charles L.
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438701, H01L 2176
Patent
active
057958149
ABSTRACT:
In a method for forming a groove-type isolation area, an insulating pattern is formed by a selective oxidation process or a LOCOS process on a semiconductor substrate. The semiconductor substrate is etched with a mask of the insulating pattern to create a groove in the semiconductor substrate. An insulating layer is buried in the groove to form the groove-type isolation area.
REFERENCES:
patent: 4449287 (1984-05-01), Maas et al.
patent: 4868136 (1989-09-01), Ravaglia
patent: 5004703 (1991-04-01), Zdebel et al.
patent: 5096848 (1992-03-01), Kawamura
patent: 5120675 (1992-06-01), Pollack
patent: 5169491 (1992-12-01), Doan
patent: 5229316 (1993-07-01), Lee et al.
patent: 5231046 (1993-07-01), Tasaka
patent: 5290396 (1994-03-01), Schoeborn et al.
patent: 5449314 (1995-09-01), Meikle et al.
Wolf, Stanley Silicon Processing For The VLSI Era, vol. 1, pp. 532-534 (1986).
Wolf, Stanley Silicon Processing For The VLSI Era, vol. 2 pp. 32-33 (1990).
Bowers Jr. Charles L.
NEC Corporation
Whipple Matthew
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