Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2008-05-09
2010-12-28
Maldonado, Julio J (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S222000, C438S424000, C257SE21546, C257SE21550
Reexamination Certificate
active
07858489
ABSTRACT:
A semiconductor device capable of selectively applying different stresses for increasing current drivability of PMOS transistor is made by defining trenches in a semiconductor substrate having a PMOS region; forming selectively a buffer layer on sidewalls of the trenches; forming an insulation layer to fill the trenches; annealing the semiconductor substrate such that compressive stress is applied in a channel length direction of a PMOS transistor by oxidizing the buffer layer; removing portions of the insulation layer and thereby forming an isolation layer; and forming the PMOS transistor on the PMOS region of the semiconductor substrate.
REFERENCES:
patent: 6251735 (2001-06-01), Lou
patent: 6326282 (2001-12-01), Park et al.
patent: 7208812 (2007-04-01), Ohta
patent: 2005/0040460 (2005-02-01), Chidambarrao et al.
patent: 2007/0164325 (2007-07-01), Liao et al.
patent: 2008/0150037 (2008-06-01), Teo et al.
patent: 2008/0173930 (2008-07-01), Watanabe et al.
patent: 1020020045656 (2002-06-01), None
patent: 1020020083807 (2002-11-01), None
patent: 2006-0128621 (2006-12-01), None
patent: 2007-0036970 (2007-04-01), None
J.W. Lee, et al; “Improvement of Data Retention Time in DRAM using Recessed Channel Array Transistors with Asymmetric Channel doping for 80 nm feature size and beyong”, ESSDERC, 2004, pp. 449-452.
Scott E. Thompson, et al; “A 90-nm Logic Technology Featuring Strained-Silicon”, IEEE Transactions on Electron Devices, vol. 51, No. 11, Nov. 2004, pp. 1790-1797.
Deok-Hyung Lee, et al; “Fin-Channel-Array Transistor (FCAT) Featuring Sub-70nm Low Power and High Performance DRAM”, IEDM Tech. Dig., 2003, pp. 407-410.
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Maldonado Julio J
LandOfFree
Method for manufacturing semiconductor device capable of... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device capable of..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device capable of... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4174512