Method for manufacturing semiconductor device and apparatus...

Semiconductor device manufacturing: process – Chemical etching

Reexamination Certificate

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C438S672000, C438S697000, C438S691000, C438S692000

Reexamination Certificate

active

06908860

ABSTRACT:
The object of the invention is to provide a method of manufacturing a semiconductor device and a processing apparatus for planarization wherein to form copper wiring in multiple layers. The removal of a residue of polishing by local electro polishing, the enhancement of the performance of planarization by using a grindstone and the reduction by small frictional force in electro polishing of damage, are enabled. To achieve the object, the following measures are taken. A residue of polishing of copper is removed by combining the detection of a local area including the residue of polishing of copper and local processing for electro polishing. As small-load processing for planarization is enabled by using electro polishing, multilayer interconnection structure using low-k material as a dielectric interlayer is also enabled. Plural pairs of small unit electrodes in a pair of which minus electrodes surround a plus electrode are provided to a tool for electro polishing, each electrode is connected to a power supply, pulse voltage is applied to each electrode and copper is electrolytically polished.

REFERENCES:
patent: 6379223 (2002-04-01), Sun et al.
patent: 6440295 (2002-08-01), Wang
patent: 6472314 (2002-10-01), Catabay et al.
patent: 6739951 (2004-05-01), Sun et al.
patent: 6743645 (2004-06-01), Kubota et al.
patent: 02-278822 (1990-11-01), None
patent: 08-083780 (1996-03-01), None
Koinkar, Vilas, et al. “Chemical Mechanical Planarization of Copper Interconnects Using Fixed Abrasive Polishing Pad,” CMP-MIC Conference, Mar. 2-3, 2000, pp. 58-65, USA.

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