Semiconductor device manufacturing: process – Making passive device – Resistor
Reexamination Certificate
2001-09-25
2004-08-31
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making passive device
Resistor
Reexamination Certificate
active
06784066
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to the formation of a transistor having an LDD structure and to the subsequent deposition of an interlayer dielectric.
2. Description of the Background Art
A system LSI (hereinafter called a DRAM-mixed device) mixed with a DRAM and a logic LSI has heretofore been manufactured. In a process for manufacturing the DRAM-mixed device, a transistor having an LDD structure and a transistor having a salicide structure have suitably been formed.
A conventional method of manufacturing a semiconductor device will be described below.
FIGS. 7A through 7K
are cross-sectional views for describing a conventional method of manufacturing a semiconductor device.
As shown in
FIG. 7A
, an element isolating oxide film
2
is first formed on a semiconductor substrate
1
. Here, the semiconductor substrate
1
has a DRAM area
101
and a logic area
102
. The logic area
102
has a first logic area
102
a
and a second logic area
102
b
. An Nch transistor is formed in the first logic area
102
a
, and a Pch transistor is formed in the second logic area
102
b.
Next, gate electrodes
3
each comprised of a gate oxide film and a polysilicon film are formed on the semiconductor substrate
1
.
An n-type impurity is implanted in the DRAM area
101
and the first logic area
102
a
of the semiconductor substrate
1
in low concentrations to thereby form N-type source/drain regions
4
and
5
respectively. Further, a p-type impurity is implanted in the second logic area
102
b
in low concentrations to thereby form P-type source/drain regions
6
.
Next, as shown in
FIG. 7B
, a silicon oxide film
7
is formed on the whole surface of the semiconductor substrate
1
, and a silicon nitride film
25
is formed on the silicon oxide film
7
.
Next, as shown in
FIG. 7C
, the silicon nitride film
25
and the silicon oxide film
7
are anisotropically etched to thereby form sidewalls
26
on the sides of the gate electrodes
3
respectively.
Next, as shown in
FIG. 7D
, resist patterns
11
, which cover areas other than the first logic area
102
a
, are formed by a photolithography technique. Further, N
+
source/drain regions
12
are formed by implanting an n-type impurity in the first logic area
102
a
in high concentrations. Afterwards, the resist patterns
11
are removed.
Next, as shown in
FIG. 7E
, resist patterns
13
, which cover ones other than the second logic area
102
b
, are formed by the photolithography technique. Further, P
+
source/drain regions
14
are formed by implanting a p-type impurity in the second logic area
102
b
in high concentrations.
Then, as shown in
FIG. 7F
, the resist patterns
13
are removed. Thus, a transistor having an LDD structure is formed in the logic area
102
.
Next, as shown in
FIG. 7G
, a silicon oxide film, which serves as a salicide protection film
15
, is formed on the entire surface of the semiconductor substrate
1
.
Subsequently, as shown in
FIG. 7H
, a resist pattern
16
, which covers the second logic area
102
b
, is formed by the photolithography technique. The salicide protection film
15
formed in each of the DRAM area
101
and the first logic area
102
a
is removed by wet etching with the resist pattern
16
as a mask. Thereafter, the resist pattern
16
is removed.
Next, a metal film, which has high melting-point, such as Co (cobalt) or the like is formed over the entire surface of the semiconductor substrate
1
. The semiconductor substrate
1
is heat-treated (annealed) at a high temperature. Further, the unnecessary metal films are removed. Thus, metal silicide films
17
having high melting-point are formed as shown in FIG.
7
I.
Next, as shown in
FIG. 7J
, a silicon nitride film
18
, which serves as an etching stopper for SAC (Self Align Contact) formation, is formed over the entire surface of the semiconductor substrate
1
.
Finally, as shown in
FIG. 7K
, a silicon oxide film used as an interlayer dielectric
19
is formed on the silicon nitride film
18
, and thereafter the semiconductor substrate
1
is heat-treated (annealed).
In the aforementioned conventional method of manufacturing a semiconductor device, however, the sidewalls each having a predetermined thickness are formed even on the sides of the gate electrodes
3
in the DRAM area
101
to form the transistor having the LDD structure in the logic area
102
. Therefore, a problem arises in that the interval between the gate electrodes
3
adjacent to one another in the DRAM area
101
becomes narrow. Further, since it is necessary to form the silicon nitride film
18
for the SAC formation after the formation of the sidewalls, the interval between the adjacent gate electrodes
3
is further narrowed.
Further, a problem arises in that when the interval between the gate electrodes
3
is narrow as described above, the interlayer dielectric
19
cannot be embedded between the gate electrodes
3
with no space. Therefore, the present method is accompanied by the problem that cavities
27
are defined between the respective gate electrodes
3
in the DRAM
101
as shown in FIG.
7
K.
While the contact holes each extending from the surface of the interlayer dielectric
19
to the surface of the semiconductor substrate
1
lying between the gate electrodes
3
are formed on a self-alignment basis after the deposition of the interlayer dielectric
19
, the following problems have been posed due to the cavities
27
.
A problem arises in that since the cavities extend frontward or in their deep directions in
FIG. 7K
, the contacts adjacent to one another frontward or in their deep directions are short-circuited. Thus, the semiconductor device (DRAM-mixed device) manufactured by the conventional manufacturing method is accompanied by a problem that a DRAM does not operation in the normal manner.
SUMMARY OF THE INVENTION
The present invention has been conceived to solve the previously-mentioned problems and a general object of the present invention is to provide a novel and useful method of manufacturing a semiconductor device, and is to a novel and useful semiconductor device manufactured by the method.
The above object of the present invention is attained by a following resist component and a following method for manufacturing a semiconductor device.
A more specific object of the present invention is to form an interlayer dielectric without any space even in an area in which the intervals between respective gate electrodes are narrow.
The above object of the present invention is attained by a following method of manufacturing a semiconductor device.
According to first aspect of the present invention, the method of manufacturing a semiconductor device having a first area, a second area and a third area on a semiconductor substrate comprises: a step of forming plurality of gate electrodes on the semiconductor substrate, each of the gate electrodes having a gate oxide film and a conductive film; a step of forming a first insulating film on the whole surface of the semiconductor substrate so as to cover the plurality of gate electrodes; a step of forming a second insulating film on the first insulating film; a step of forming sidewalls on the sides of the plurality of gate electrodes respectively by means of etching the first insulating film and the second insulating film, each of the sidewalls including a layer for the first insulating film covering the sides of the gate electrodes and a layer for the second insulating film covering the layer for the first insulating film; an impurity implanting step of implanting an impurity in the second area and the third area with the sidewalls as masks; a first removing step of removing the layer for the second insulating film formed on the sides of the gate electrodes after the impurity implanting step; a third insulating film forming step of forming a third insulating film on the whole surface of the semiconductor substrate after the first remov
Chaudhuri Olik
Kebede Brook
McDermott & Will & Emery
Renesas Technology Corp.
LandOfFree
Method for manufacturing semiconductor device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3355840