Method for manufacturing semiconductor device

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing

Reexamination Certificate

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C716S130000

Reexamination Certificate

active

08006217

ABSTRACT:
To reduce current consumption in a frequency-division circuit, particularly in a multistage frequency-division circuit, in a multistage frequency-division circuit, an inputted signal has a higher frequency in a preceding stage, and an inputted signal has a lower frequency in a following stage. Thus, placement is performed preferentially from the basic cell corresponding to the frequency-division circuit into which a signal having a higher frequency is inputted, and then wiring connection is performed. In other words, the layout of a plurality of basic cells corresponding to a multistage frequency-division circuit is performed so that, as compared to a wiring into which a signal having a lower frequency is inputted, a wiring into which a signal having a higher frequency is inputted has a shorter wiring length and has less intersection with other wirings, so that parasitic capacitance and parasitic resistance of the wiring are reduced.

REFERENCES:
patent: 2005/0138507 (2005-06-01), Kurokawa
patent: 2007/0036237 (2007-02-01), Kobayashi et al.
patent: 2007/0285246 (2007-12-01), Koyama
patent: 7-66254 (1995-03-01), None
patent: 2005-184608 (2005-07-01), None
patent: 2008-9972 (2008-01-01), None
patent: WO 2007/139205 (2007-12-01), None
International Search Report re application No. PCT/JP2009/066841, dated Oct. 20, 2009.
Written Opinion re application No. PCT/JP2009/066841, dated Oct. 20, 2009.

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