Semiconductor device manufacturing: process – Making device array and selectively interconnecting
Reexamination Certificate
2009-12-28
2010-10-05
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
C438S129000, C438S532000, C438S599000, C257SE21585, C257SE21658, C257SE21660
Reexamination Certificate
active
07807513
ABSTRACT:
Methods for manufacturing a semiconductor device are provided that reduces the thickness of an oxide layer formed on a polysilicon layer for bit line contacts. A reduced thickness oxide layer can prevent short circuits between adjoining bit lines. A reduced thickness oxide layer can also eliminate the need for overetching in a subsequent etching process, thereby preventing loss of an isolation layer in a peripheral region.
REFERENCES:
patent: 6326657 (2001-12-01), Ohkawa
Joung Yong Soo
Kim Hyung Kyun
Garber Charles D
Hynix / Semiconductor Inc.
Ladas & Parry LLP
Lee Cheung
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