Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2006-05-30
2006-05-30
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S624000, C438S763000
Reexamination Certificate
active
07052971
ABSTRACT:
A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.
REFERENCES:
patent: 6024106 (2000-02-01), Yang et al.
patent: 6335287 (2002-01-01), Hwang et al.
patent: 6335288 (2002-01-01), Kwan et al.
patent: 6380047 (2002-04-01), Bandyopadhyay et al.
patent: 6391781 (2002-05-01), Ozawa et al.
patent: 6395150 (2002-05-01), Van Cleemput et al.
patent: 6417073 (2002-07-01), Watanabe
patent: 6448150 (2002-09-01), Tsai et al.
patent: 6740601 (2004-05-01), Tan et al.
patent: 2002/0055271 (2002-05-01), Lee et al.
patent: 2003/0162363 (2003-08-01), Ji
patent: 2004/0126952 (2004-07-01), Gondhalekar et al.
patent: 2004/0198019 (2004-10-01), Yasui et al.
patent: 59-058837 (1984-04-01), None
patent: 59-225543 (1984-12-01), None
patent: 2000-114362 (2000-04-01), None
patent: 2000-183150 (2000-06-01), None
patent: 2000-294627 (2000-10-01), None
patent: 2000-332099 (2000-11-01), None
patent: 2001-135718 (2001-05-01), None
patent: 2001-244327 (2001-09-01), None
patent: 2003031650 (2003-01-01), None
Derwent Acc No. 2002-596241: Abstract of KR2002017588A.
Derwent Acc No. 2002-748804: Abstract of KR2002046828A.
Notification of Reason for Rejection issued by Japanese Patent Office, mailed Sep. 6, 2005, in Japanese Patent Application No. 2001-213689, and English-language translation.
Nakata Rempei
Nishiyama Yukio
Ogihara Hirotaka
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Fourson George
Kabushiki Kaisha Toshiba
LandOfFree
Method for manufacturing semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method for manufacturing semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for manufacturing semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3568818