Semiconductor device manufacturing: process – Chemical etching – Liquid phase etching
Reexamination Certificate
2003-06-13
2004-11-30
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Liquid phase etching
C438S424000, C438S425000, C438S435000, C438S700000, C438S704000
Reexamination Certificate
active
06825128
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to the method for manufacturing the semiconductor device by which an element isolation region is formed utilizing an STI (Shallow Trench Isolation) method.
The present application claims priority of Japanese Patent Application No. 2002-174094 filed on Jun. 14, 2002, which is hereby incorporated by reference.
2. Description of the Related Art
Large Scale Integrations (LSIs) known as a representative of semiconductor devices are roughly classified into memory devices and logic devices, most of which are made up of Metal Oxide Semiconductor (MOS) type transistors are excellent in integration density. By thus manufacturing the LSI using the MOS type transistor as a component unit, an advantage in improvements of the integration density can be utilized greatly, thereby reducing costs of the LSI.
When manufacturing the LSI, in order to insulate and isolate semiconductor regions (active regions) from each other in each of which elements (the MOS type transistors) are to be formed, an element isolation region is formed on a semiconductor substrate beforehand. To form such the element isolation region, conventionally a method of Local Oxidation of Silicon (LOCOS) has been used commonly. The element isolation region formed by this LOCOS method, however, occupies a relatively large area inevitably due to its nature in methodology to thus degrade the integration density; therefore, an STI method is employed in place of the LOCOS method recently. The STI method has a feature that the element isolation region is formed by forming a trench in the semiconductor substrate beforehand and then burying an oxide (insulating material) into the trench. By the STI method, the oxide is buried into a minute trench which is formed in a semiconductor substrate by utilizing a known photolithographic process, so that the element isolation region having a small area can be realized, thereby avoiding a decrease in the integration density.
Typically, however, if the element isolation region is formed by the STI method, as shown in
FIG. 7
, a periphery of an oxide
135
buried into a trench
132
in a semiconductor substrate
131
is etched off to thus form a hollow (depression)
133
. The hollow
133
may generate a sub-channel when subsequently a MOS type transistor, which is an element, is formed in an active region
134
, thereby giving rise to a irregular leakage current when the MOS type transistor is in an OFF state.
A semiconductor device manufacturing method for avoiding occurrence of such a hollow as described above when forming an element isolation region by thus utilizing the STI method is disclosed, for example, in Japanese Patent Application Laid-open No. 2000-323565. The semiconductor device manufacturing method (first conventional method) is described in sequence of processes with reference to
FIGS. 4A
to
4
G.
First, as shown in
FIG. 4A
, on a silicon substrate
101
, an oxide film
102
(undercoating film) made of a silicon oxide and a silicon nitride film
103
are formed and stacked sequentially. Next, as shown in
FIG. 4B
, after the silicon nitride film
103
and the oxide film (undercoating film)
102
in an element isolation region formation-expected region are selectively etched off by anisotropic etching, the silicon substrate
101
is selectively etched off using the silicon nitride film
103
as a mask, to form a trench
104
.
Next, as shown in
FIG. 4C
, the silicon nitride film
103
undergoes a pullback (backing-off) type of isotropic etching (hereinafter referred to as pullback etching) using hot phosphoric acid, to form therein an opening
105
having a width W1 larger than a width W2 of an opening of the trench
104
. Next, as shown in
FIG. 4D
, a buried oxide film
106
made of a silicon oxide film is formed over (on) all of the silicon substrate
101
, the oxide film
102
, the silicon nitride film
103
and the trench
104
by Chemical Vapor Deposition (CVD) method.
Next, as shown in
FIG. 4E
, the buried silicon oxide film
106
is polished so as to be thinner by Chemical Mechanical Polishing (CMP) using the silicon nitride film
103
as a stopper layer. Next, as shown in
FIG. 4F
, the silicon nitride film
103
is etched off using hot phosphoric acid. As a result, the buried silicon oxide film
106
, which is already present in the opening
105
formed in the silicon nitride film
103
by pullback etching as shown in the step of
FIG. 4C
, is left as partially spreading over the oxide film (undercoating film)
102
, so that such a hollow as described above is not formed. Further, by forming the opening
105
by pullback etching, it is possible to improve a degree of the oxide buried film
106
being buried into the trench
104
. In this case, processing is performed so that a width “a” and a height “b” of the spread may be larger than a film thickness of the oxide film
102
. Next, as shown in
FIG. 4G
, the oxide film
102
is selectively etched off by wet etching using hydrofluoric acid, to form an element isolation region
108
.
In a case where the element isolation region
108
is formed by the first conventional technology described above, although it is possible to avoid such formation of the hollow as described above, a surface of the trench
104
in the silicon substrate
101
is exposed when the silicon nitride film
103
is pullback-etched in a step of FIG.
4
C and so roughly etched, which is a disadvantage.
To eliminate this disadvantage, such a semiconductor device manufacturing method is provided that in a case of forming an element isolation region by utilizing an STI method, a trench surface is protected by an insulation film when a silicon nitride film undergoes pullback etching. The following will describe the semiconductor device manufacturing method (second conventional method) in sequence of processes with reference to
FIGS. 5A-5H
.
First, as shown in
FIG. 5A
, on a silicon substrate
111
, a silicon oxide film
112
and a silicon nitride film
113
are formed and stacked sequentially beforehand. Then, the silicon nitride film
113
and the silicon oxide film
112
which are present on an element isolation region formation-expected region (not labeled or shown) are selectively etched off. And then, the silicon substrate
111
is selectively etched off by plasma etching method using the silicon nitride film
113
as a mask to thus form therein a trench
114
having a depth of about 300 nm. Next, as shown in
FIG. 5B
, by heating the silicon substrate
111
to about 950° C. by wet oxidation to perform rounding oxidation in order to round an edge of the trench
114
in the silicon substrate
111
, a silicon oxide film
115
having a film thickness of about 20 nm is formed on a surface of the trench
114
. This silicon oxide film
115
undertakes a role of covering the surface of the trench
114
to protect it when the silicon nitride film
113
undergoes pullback etching subsequently. It is to be noted that during the rounding oxidation, a surface of the silicon nitride film
113
is also oxidized slightly simultaneously to thus have a thin silicon oxide film
116
formed thereon. In this case, a ratio in film thickness between the silicon oxide film
115
and the thin silicon oxide film
116
is about 20-25:1.
Next, as shown in
FIG. 5C
, by performing wet etching using an etchant containing hydrofluoric acid for about one minute, the thin silicon oxide film
116
on the surface of the silicon nitride film
113
is etched off as pre-pullback processing. This etching of the thin silicon oxide film
116
is performed in order to stabilize the subsequent pullback etching of the silicon nitride film
113
by use of hot phosphoric acid. That is, since a selective ratio between the silicon nitride film
113
and the silicon oxide film
112
is high, the thin silicon oxide film
116
, if any on the surface of the silicon nitride film
113
, blocks etching of the silicon nitride film
113
, so
Goudreau George A.
NEC Electronics Corporation
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