Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor
Reexamination Certificate
2003-07-30
2004-12-28
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
C438S108000, C438S119000
Reexamination Certificate
active
06835593
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor device having a Chip-On-Chip structure in which a semiconductor chip is bonded onto another semiconductor chip.
2. Description of Related Art
One form of so-called a multi-chip type semiconductor device has a Chip-On-Chip structure in which a plurality of semiconductor chips are stacked. In a semiconductor device having a Chip-On-Chip structure, a sub-chip smaller than a main chip is bonded onto a surface of the main chip connected to outside. In some cases, a plurality of sub-chips are bonded onto a main chip.
Each of the main chip and the sub-chip has a plurality of metal bumps on its active surface provided with functional elements and wirings thereon. These metal bumps are mainly formed of a high melting point metal such as gold (Au), and a layer of a low melting point metal such as tin (Sn) is formed on each of the top portions of both or either of metal bumps of the main chip and the metal bumps of the sub-chip.
In a first conventional method for manufacturing a semiconductor device having a Chip-On-Chip structure, the active surface of the main chip and the active surface of the sub-chip are opposed to each other and the main chip and the sub-chip are heated to a temperature higher than the melting point (solidus temperature) of the low melting point metal. Thereby, the low melting point metal layers formed on the top portions of the metal bumps melt. Thereafter, the metal bumps of the main chip and the metal bumps of the sub-chip are positioned with respect to each other and brought close to (into contact with) each other, and the main chip and the sub-chip are cooled to a temperature lower than the melting point of the low melting point metal. As a result, the low melting point metal solidifies, and the metal bumps of the main chip and the metal bumps of the sub-chip are electrically and mechanically bonded together through the low melting point metal.
In a second conventional method for manufacturing a semiconductor device having a Chip-On-Chip structure, a load is applied on the main chip and the sub-chip so that the metal bumps of the main chip and the metal bumps of the sub-chip can be pressed against each other, and then the main chip and the sub-chip are heated to a temperature higher than the melting point (solidus temperature) of the low melting point metal. Thereby, the low melting point metal layers formed on the top portions of the metal bumps respectively melt. Thereafter, the main chip and the sub-chip are cooled to a temperature lower than the melting point of the low melting point metal. As a result, the low melting point metal solidifies, and the metal bumps of the main chip and the metal bumps of the sub-chip are electrically and mechanically bonded together through the low melting point metal.
In this case, if oxide films are formed on the surfaces of the metal bumps of the main chips and the metal bumps of the sub-chips, the oxide films are broken by pressing the metal bumps of the main chip and the metal bumps of the sub-chips against each other, so that the metal bumps of the main chip and the metal bumps of the sub-chip can be suitably bonded through the low melting point metal.
The abovementioned bonding may be carried out with the use of, instead of the main chip, a wafer before main chips are cut out therefrom. In this case, after the semiconductor wafer and the sub-chips are bonded together, the semiconductor wafer is cut into pieces of semiconductor chips each having a Chip-On-Chip structure.
However, in the abovementioned first manufacturing method, when the metal bumps of the main chip and the metal bumps of the sub-chips are brought close to each other, the molten low melting point metal is pushed out from between the metal bumps of the main chip and the metal bumps of the sub-chips respectively and flow sideways. Thereby, adjacent metal bumps are electrically short-circuited in an extreme case.
Further, in the case of carrying out such bonding using a semiconductor wafer instead of a main chip according to the abovementioned method, a number of (e.g. thousands of) sub-chips are bonded onto the semiconductor wafer. Consequently, the wafer and the sub-chips are in the over-heated state to a high temperature for a long time till all of the sub-chips are bonded. Thereby, the characteristics of the main chips and the sub-chips are degraded.
Further, a semiconductor wafer has a number of (thousands of) regions each corresponding to a main chip, and therefore, it is impossible to press sub-chips against all of the regions each corresponding to a main chip at one time and heat them. Therefore, in the abovementioned second manufacturing method, it is necessary to transfer a sub-chip to a predetermined position above the semiconductor wafer by means of a vacuum collet, heat and cool the same with applying a load on the sub-chip and repeat these steps as many times as the number of the sub-chips. This results in a low productivity.
Further, at the time of bonding the main chip and the sub-chip together, the metal bumps of the main chip and the metal bumps of the sub-chip are required to be accurately positioned with respect each other. However, a device used for bonding gets out of order because of its heat history accompanied by heating and cooling, so that the accuracy of the positioning cannot be made high.
Furthermore, at the time of bonding the main chip and the sub-chip, for example, if the sub-chip are electrically charged, the functional elements on the main chip are electrostatically damaged by electric discharge from the sub-chip when the metal bumps of the main chip and the metal bumps of the sub-chip come into contact with each other. In order to prevent such damage from occurring, the main chip is provided with a protective diode connected to the metal bumps. However, such a protective diode in itself is unnecessary, and if such a protective diode is provided, the area used for forming other functional elements is reduced.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method for manufacturing a semiconductor device capable of suitably bonding together metal bumps formed on a first semiconductor substrate and metal bumps formed on a second semiconductor substrate respectively.
Another object of the present invention is to provide a method for manufacturing a semiconductor device in which characteristics of the semiconductor substrates are hard to be degraded.
A further object of the present invention is to provide a method for manufacturing a semiconductor device having a high productivity.
A further object of the present invention is to provide a method for manufacturing a semiconductor device capable of bonding a plurality of semiconductor substrates with reducing unalignment or displacement thereof.
A further object of the present invention is to provide a method for manufacturing a semiconductor device in which it is unnecessary to provide a protective diode on a semiconductor substrate for preventing electrostatic damage from occurring at the time of bonding a plurality of semiconductor substrates.
A method for manufacturing a semiconductor device according to a first aspect of the present invention is a method for manufacturing a semiconductor device by bonding a first metal bump formed on a first semiconductor substrate and a second metal bump formed on a second semiconductor substrate. This method includes a low melting point metal layer forming step for forming a low melting point metal layer on a top portion of at least either of the first metal bump and the second metal bump, a substrate temperature controlling step for, with the first semiconductor substrate and the second semiconductor substrate being separated from each other, controlling the temperature of the first semiconductor substrate to a first temperature higher than a solidus temperature of the low melting point metal and controlling the temperature of the second semiconductor substrate to a second temperatu
Dang Trung
Rabin & Berdo P.C.
Rohm & Co., Ltd.
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