Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-11-17
2002-11-12
Ho, Hoai (Department: 2818)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S417000
Reexamination Certificate
active
06479306
ABSTRACT:
TECHNICAL FIELD
The invention relates to a semiconductor device mounted on a memory substrate, a mother board, or the like and a method for manufacturing the same.
BACKGROUND ART
A semiconductor chip such as a memory chip cut out from a semiconductor wafer is generally mounted on a printed substrate or the like in a packaging condition. However, an outer size of a package is considerably larger than the size of a various types of the semiconductor chips themselves and therefore, there is a certain limit in the number of the packages mountable on the printed substrate or the like.
On the other hand, recently, a multichip module (MCM), in which a plurality of semiconductor chips are mounted on the substrate, is being popularized. Using the multichip module allows the followings: (1) miniaturization of a mounting area and weight reduction accompanying with this, (2) realization of a high performance and high speed by high density wiring and bear chip mounting, and (3) keeping high reliability.
By the way, in the multichip module capable of a high density mounting described above, a plurality of semiconductor chips are mounted on a single substrate and therefore, a defect ratio of respective semiconductor chip is accumulated to make a total defect ratio of the module large. For example, in the case where two semiconductor chips are implemented on a single module substrate, only one defect semiconductor chip causes overall defect of the module. Therefore, it is necessary handling to replace the defect semiconductor chip as a repairing work and discard the overall module as a defect product. Thus, a low yield and a low efficiency occur. In addition, in the case where a plurality of semiconductor chips are mounted on a single substrate, each one of respective chips is mounted on a single substrate to complicate a manufacturing process.
DISCLOSURE OF THE INVENTION
The present invention is achieved in consideration of such points and an object thereof is to provide a semiconductor device and a method for manufacturing thereof capable of reducing a defect ratio in manufacturing the semiconductor device mountable with high density and capable of simplifying the process.
In the present invention, after a plurality of different kinds of semiconductor chips are formed on the semiconductor wafer or after wiring, resin sealing, and terminal formation is carried out for these semiconductor chips, a go
o-go test (quality test) is conducted for each semiconductor chip. According to the result, a unit of predetermined of a plurality of semiconductor chips is divided to form the semiconductor device. Dividing semiconductor chips is carried out according to the result of quality test. When the semiconductor device comprising a plurality of semiconductor chips is manufactured, some defective semiconductor chips among them does not cause defect of overall semiconductor device. Thus, the defect rate in manufacturing the semiconductor device can be reduced. Because the semiconductor device comprising a plurality of semiconductor chips can be used in a process thereafter and thus, in comparison with application of combination of a plurality of semiconductor devices comprising a single semiconductor chip, the process thereafter can be simplified.
Particularly, by practice of a mounting step composed of wiring, resin sealing, and terminal formation for respective semiconductor chips formed on the semiconductor wafer, in comparison with the case where the mounting step is carried out after respective semiconductor chips are individually divided more simplification of the process become possible.
REFERENCES:
patent: 5391916 (1995-02-01), Kohmo et al.
patent: 6281026 (2001-08-01), Ikeda et al.
patent: 6291309 (2001-09-01), Ikeda et al.
patent: 49-355860 (1974-09-01), None
patent: 6-334034 (1994-12-01), None
patent: 9-199450 (1997-07-01), None
Ikeda Kouichi
Ikeda Takeshi
Dellett and Walters
Ho Hoai
Le Thao P
Niigata Seimitsu Co., Ltd.
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