Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2000-03-28
2002-06-11
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S425000, C438S435000, C148SDIG005
Reexamination Certificate
active
06403446
ABSTRACT:
BACKGROUND OF THE INVENTION
A SGI(Shallow Groove Isolation) structure is a structure which electrically insulates adjoining transistor on a semiconductor substrate. The SGI structure is formed following processes. Forming a groove at a silicon substrate forming a pad oxide film on the silicon substrate forming an oxidation inhibition film on the pad oxide film and afterwards. thermally oxidize the surface of the groove to form an element isolation thermal oxide film on the surface of the groove and burying in the groove an insulating film. Further formed thereon are several films including a gate oxide film a gate electrode film a dielectric film, a lead an interlayer dielectric film and so on to thereby obtain a semiconductor device.
This SGI structure becomes the suitable structure in the device after the 0.25 &mgr;m process because dimensional accuracy of the SGI structure is higher than conventional LOCOS(Local Oxidation of Si) structure of which has been used more than 0.25 &mgr;m process. However. when thermally oxidize the surface of the groove to form the element isolation thermal oxide film, there is a case that the groove upper edge becomes acute angle. Such acute angled part remain of the groove upper edge, as A. Bryant et al disclosed in “Technical Digest of IEDM′94.pp.671-674” an electric field concentration arises at the acute angled part under circuit operation. and. there is a case that decline in characteristics of transistors and voltage characteristics of capacitors.
As a solution of these problems JP-A-2-260660 disclose that before thermally oxidize the surface of the groove to form an element isolation thermal oxide film, remove the pad oxide film about 0.1 &mgr;m from sidewall in the groove upper edge. And after that, by oxidizing at the temperature about 1000° C. with a steam. to roundly form the the groove upper edge.
SUMMARY OF THE INVENTION
Above method (JP-A-2-260660) could roundly form the groove upper edge but characteristics of transistors could not be improved.
The inventor analyze the reason why the characteristics of transistors could not be improved by above method (JP-A-2-260660) and the following was discovered as a result of analyzingsis. Above method (JP-A-2-260660) is useful to roundly form the groove upper edge but there is a case that substrate level difference arose in the silicon substrate upper surface because in the exposed region by pad oxide film removal. the oxidation progresses in comparison with not removal region.
The gate oxide film thickness becomes unequal when the gate oxide film is formed in such level difference so electrical weak spots is formed and stress concentration occur. Therefore, characteristics of transistors formed on the level difference decline.
An object of the present invention to provide a novel and improved method for manufacturing a semiconductor device capable of avoiding the problems faced with the prior art.
In order to achieve the purpose inventor did experiments and analyses and then the inventor found following contents.
1) Removing the pad oxide film along the substrate surface from the upper edge of the groove over a distance ranging from 5 to 40 nm to prevent creation of level difference at or near the upper groove edges while simultaneously increasing the radius curvature thereat to go beyond a specified value.
As the removal of the pad oxide film becomes greater in value from 0 nm the radius curvature at the upper substrate edges increases accordingly. The radius curvature becomes about 15 nm when the removal amount is 5 nm. When the removal is set at 20 nm the radius curvature increase about 25 nm. Note however that if the removal amount is excessively increased not less than 40 nm the resulting radius curvature behaves to decrease rather than increase. This would result in occurrence of the level difference at or near the upper groove edges.
Accordingly, forcing the pad oxide film to remove from the upper edges of the groove within a limited range of from 5 to 40 nm may enable elimination of generation of level differences at or near such groove edges while at the same time enabling the radius curvature at the groove edges to increase beyond a predetermined value.
2) Removing the exposed surface of the semiconductor substrate by isotropic etching methods within a range of more than 0 nm and not more than 20 nm. And so above method may eliminate creation of the level difference.
The curvature radius in the groove upper edge is approximately at 15 nm when the silicon etching quantity is 0 nm, and is about 30 nm when the etching amount is between 10 and 20 nm. In a region with the etching amount greater than 20 nm the level difference can reside at the “upper” groove edge portions. This makes the radius curvature tend to decrease below 20 nm.
Upon occurrence of the level difference at or near the upper groove edge the fabrication of a gate oxide film fails to exhibit uniformity resulting in production of electrical weak spots therein. In this respect, setting the upper limit of the silicon substrate etching amount at such specific value 20 nm makes it possible to prevent creation of any level difference on the substrate.
3) Oxidizing a groove portion formed in said semiconductor substrate in an oxidation environment with a gas ratio of hydrogen (H
2
) to oxygen (O
2
) being less than or equal to 0.5. And so, above method permits the intended oxidation to progress under lower stresses at the upper groove edges of the semiconductor substrate thereby enabling achievement of rounding of the upper groove edges of silicon substrate.
Oxidation causes deformation (stress) near or around the interface between silicon and the silicon oxide film. On the other hand, the silicon oxide film exhibits significant viscosity behavior at high temperatures (900° C. or above). Thus any stresses generated will become less intense with time.
Consequently, assuming that the oxide film thickness stays constant the residual stresses generated becomes increased. This can be said because although the generated deformation (stress) might be kept constant in value, a time taken for the generated stress to relax is shortened with an increase in oxidation rate (namely. increase in H
2
/O
2
gas ratio).
In cases where the oxidation rate is low (i.e. the H
2
/O
2
gas ratio r is small). the silicon oxide films viscosity effect becomes operative accelerating relative stress relaxation while the oxide film thickness is kept unchanged. The stronger the oxidation induction stresses the greater the suppression of oxidation at part near or around it. Accordingly, in view of the fact that the upper groove edges of silicon substrate or its nearby regions are the location whereat stresses attempt to locally concentrate during growth of an oxide film bidirectionally from both its upper surface and the lateral surfaces thereof the higher the residual stresses the more effective the suppression of oxidation near this location. This results in the edges becoming sharpened more and more at their tip ends.
In light of the foregoing, reducing the H
2
/O
2
gas ratio r permits the intended oxidation to progress under lower stresses at the upper groove edges of the semiconductor substrate
1
thereby enabling achievement of rounding of the upper groove edges of silicon substrate.
Suppose that an Ar gas or N
2
gas is introduced into a furnace with the H
2
/O
2
gas ratio r kept constantly at 1.8 to thereby effectuate dilution approximately 0.6 times. The resulting oxidation rate is nearly equal to the value 0.5 of the H
2
/O
2
gas ratio r. This in turn to achieve the intended radius curvature of 3 nm even under the condition that the H
2
/O
2
gas ratio r is 1.8.
REFERENCES:
patent: 4580330 (1986-04-01), Pollack et al.
patent: 5258332 (1993-11-01), Horioka et al.
patent: 5578518 (1996-11-01), Koike et al.
patent: 5719085 (1998-02-01), Moon et al.
patent: 5863827 (1999-01-01), Joyner
patent: 5956598 (1999-09-01), Huang et al.
patent: 6090684 (2000-07-01), Ishitsuka et al.
patent: 2-260660 (1990-10-01), None
patent: 7-74164 (1995-03-01)
Funayama Kota
Ikeda Shuji
Ishitsuka Norio
Kojima Masayuki
Miura Hideo
Dang Trung
Mattingly Stanger & Malur, P.C.
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