Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1983-06-14
1984-11-27
Saba, William G.
Metal working
Method of mechanical manufacture
Assembling or joining
29576E, 29576W, 29577C, 29578, 148175, 148187, 148188, 156653, 156657, 156662, 357 43, 357 48, 357 49, H01L 21225, H01L 2120, H01L 2176
Patent
active
044843887
ABSTRACT:
A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n.sup.+ -type buried layers therein, n-type wells are formed to extend to the n.sup.+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region. Gate electrodes of the CMOS are formed and have a low resistance due to doping with phosphorus and/or arsenic. Using the emitter electrode as a diffusion source, an n-type emitter region is formed. Boron is then ion-implanted to simultaneously form a p.sup.+ -type external base region and p.sup.+ -type source and drain regions of the p-channel MOS transistor. Phosphorus is ion-implanted to form an n.sup.+ -type collector contact region and n.sup.+ -type source and drain regions of the n-channel MOS transistor.
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Saba William G.
Tokyo Shibaura Denki Kabushiki Kaishi
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